iMX7ULP M4 clock configuration with SDK functions

[markus4work]

In my project, I start with the clock configuration the Boot ROM provides:

MCU running on FIRC @48MHz, DIV1-Platform and DIV2-BUS also @48MHz.

Now I want to configure e.g. the SIRC oscillator, Boot ROM configuration is SIRC on, but DIV1-Platform and DIV2-Bus deactivated.

I create the struct :

scg_sirc_config_t g_scgSircConfig = {.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,

.div1 = kSCG_AsyncClkDivBy1,

.div2 = kSCG_AsyncClkDivBy1,

.div3 = kSCG_AsyncClkDisable,

.range = kSCG_SircRangeHigh};

and call

CLOCK_InitSirc(&g_scgSircConfig);

to reconfigure the SIRC oscillator.

As probed with my Segger J-Link, the div1 value and the div2 value in register

SCG->SIRCDIV is not changed.

Checking the frequency with

CLOCK_GetFreq(kCLOCK_ScgSircAsyncDiv1Clk));

CLOCK_GetFreq(kCLOCK_ScgSircAsyncDiv2Clk));

gives the same result, Div1/Div2 still off.

When I call

CLOCK_SetSircAsyncClkDiv(kSCG_AsyncDiv1Clk, kSCG_AsyncClkDivBy2);

CLOCK_SetSircAsyncClkDiv(kSCG_AsyncDiv2Clk, kSCG_AsyncClkDivBy2);

afterwards, Div1/Div2 is set as expected to the chosen divider.

I monitor the same behavior for SOSC.

I need to provide a struct with the full desired configuration to

CLOCK_InitSirc(&g_scgSircConfig);

but the configuration is only set partially.

I now want to know if this behavior is intentional or a bug ?

Best regards,

Markus.

[Dhruvit]

Hi @markus4work,

I hope you are doing well.

Please mention where you are making a call to CLOCK_InitSirc().

- CLOCK_SetSircAsyncClkDiv is defined as below in SDK.

static inline void CLOCK_SetSircAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
{
    uint32_t reg = SCG->SIRCDIV;

    switch (asyncClk)
    {
        case kSCG_AsyncDiv3Clk:
            reg = (reg & ~SCG_SIRCDIV_SIRCDIV3_MASK) | SCG_SIRCDIV_SIRCDIV3(divider);
            break;
        case kSCG_AsyncDiv2Clk:
            reg = (reg & ~SCG_SIRCDIV_SIRCDIV2_MASK) | SCG_SIRCDIV_SIRCDIV2(divider);
            break;
        default:
            reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider);
            break;
    }

    SCG->SIRCDIV = reg;
}

- SIRCDIV is configured in CLOCK_InitSirc as below:

SCG->SIRCDIV =
        SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3);

So I don't think CLOCK_InitSirc implementation could be the issue.

Thanks & Regards,

Dhruvit Vasavada.