iMX6UL Reference Manual - DDR density specification

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iMX6UL Reference Manual - DDR density specification

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markusb
Contributor I

Hi,

in IMX6ULRM it say in 33.1.1 , that 256Mbits-8Gbits are the supported densities of DDR devices, however 6.2 specifies a density of 256Mbytes - 4Gbytes.

I suppose the first one is correct and there would be no issue using a 128MByte = 1Gbit device?

Thanks!

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   The i.MX6UL MMDC inludes the following features :

* x16 data bus width (2 bytes);

* up to 8 banks (3 bits );

* column size of 8–12 bits ;

* row size of 11–16 bits.

 

  So, minimal address size is 8 MBytes [2 ** (11+8+3+1)]

and maximal one is full 4GB.

 

128 MB is supported.

 

Have a great day,
Yuri

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1 Reply
214 Views
Yuri
NXP TechSupport
NXP TechSupport

Hello,

   The i.MX6UL MMDC inludes the following features :

* x16 data bus width (2 bytes);

* up to 8 banks (3 bits );

* column size of 8–12 bits ;

* row size of 11–16 bits.

 

  So, minimal address size is 8 MBytes [2 ** (11+8+3+1)]

and maximal one is full 4GB.

 

128 MB is supported.

 

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!

View solution in original post