iMX6UL DDR Init and Stres Test

[elizabethamyoun]

I am using a Micron DDR3, PN MT41K64M16TW-107 on a custom design. Attached is the modified MMDC configuration script. The DDR parameters were modified from the MCIMX6UL-EVK spreadsheet.

After initializing the DDR w/o running the calibration (or stress test) I cannot R/W to any memory address.

If I initialize, followed by a calibration test the device fails at DQS calibration (see output below). However, despite failing, I am able to R/W to any memory address.

My questions are:

1. What is the calibration doing that despite failing, I can R/W to memory?

2. The eval board uses a Micron chip with an 1866 MT/s speed rating. The timing parameters inputted in the spreadsheet are set to the 800MT/s (400Mhz clock) rating. However, the speed bins (RAS,CAS, etc) are set to the 1866 MT/s parameters. Is this correct?

3. The eval board does not implement *any* address/command termination resistors. Is this because you are using the on-die termination? My custom design has discrete address/command termination resistors on the board. Is there a register setting I should be shutting off? Could this be why I am failing the calibration test?

Also for the record, the design fails the stress test immediately (see below).

//-------------------------------

DDR Freq: 365 MHz

t0.1: data is addr test

Address of failure(step2): 0x80000000

Data was: 0xffffffff

But pattern  should match address

Error: failed to run stress test!!!

//---------------------------------------------

    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F

Write DQS delay result:

   Write DQS0 delay: 31/256 CK

   Write DQS1 delay: 31/256 CK

Starting DQS gating calibration

. HC_DEL=0x00000000     result[00]=0x00000011

. HC_DEL=0x00000001     result[01]=0x00000011

. HC_DEL=0x00000002     result[02]=0x00000011

. HC_DEL=0x00000003     result[03]=0x00000011

. HC_DEL=0x00000004     result[04]=0x00000011

. HC_DEL=0x00000005     result[05]=0x00000011

. HC_DEL=0x00000006     result[06]=0x00000011

. HC_DEL=0x00000007     result[07]=0x00000011

. HC_DEL=0x00000008     result[08]=0x00000011

. HC_DEL=0x00000009     result[09]=0x00000011

. HC_DEL=0x0000000A     result[0A]=0x00000011

. HC_DEL=0x0000000B     result[0B]=0x00000011

. HC_DEL=0x0000000C     result[0C]=0x00000011

. HC_DEL=0x0000000D     result[0D]=0x00000011

ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

Error: failed during ddr calibration

[Yuri]

Hello,

1.

 Please look at the following :

Freescale i.MX6 DRAM Port Application Guide-DDR3 

 In particular, use section 3.3.1  (Identifying Issue on Calibrations). Really calibration process provides
timing margins, that may change even for the same board for several test passes.  Customers should
find optimal solution for all possible environments.
  Some issues may be observed during testing, when memory design does not meet requirements,
therefore  it may be recommended to follow  general rules, provided for customers to simplify their PCB
considerations. General  recommendations are provided in the Development Guide, linked below.

  Hardware Development Guide for i.MX6 contains Chapter 3 (i.MX 6 Series Layout Recommendations)

< http://cache.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf  >

  Also, You may look at  section 1.1 (Schematic and Layout Design Rules) of the DDR3 Porting Guide.  In
particular, there is an Excel page named “MX6 DRAM Bus Length Check” in “HW Design Checking List  
for i.Mx6”. Designer can use it for layout self-checking. Input trace length of the design into cells in pink  
circle then, the bottom cell in same column may change to red color if layout breaks the rule.

Recent design checklist may be found at

https://community.nxp.com/docs/DOC-93819 

2.

  All memory timing parameters should be calculated, based on 400Mhz memory clock. 

3.

  According to section 3.6.2 [DDR3 (64 bits) T topology considerations] of the Hardware Development

Guide:
"Be sure to take into account the following when designing a T-topology system.
• Follow the routing rules described in Table 3-3.
• Termination resistors not required.
• Short routing lengths and on-chip drive strength control.
• Your design is limited to 4 DDR chips.
• DDR3, 2 GBytes using latest memories (4 GBytes available now)."

Have a great day,

Yuri

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