iMX6 NAND Address cycles definition

[tarterkit_ru]

Reference Manual have:

Table 8-11. NAND Boot eFUSE Descriptions: BOOT_CFG1[1:0] - Address Cycles

Fusemap Table 5-8. NAND Boot Fusemap: BOOT_CFG1[1:0] - Nand_Row_address_byte

What exactly need set to BOOT_CFG[1:0], all address cycles or only row address cycles?

[weidong_sun]

It should be all address cycles.

Regards,

Weidong

[Rodrigue]

Hi Weidong,

Are you sure? because the fuse map definition we use to have specifies the NAND row address bytes.

May you please confirm?

regards,

[Yuri · Accepted solution]

It looks like AddressCycles are Row Address Bytes, assuming Column Address Bytes = 2 

[_timm]

Hi: did we ever reach a definitive conclusion on this? I have the exact same situation: an OEM has set these fuses to 11b, but the NAND device that we are using has 2 column address bytes (fuses are 00b according to DQRM). So what is the correct answer? 

Thanks,

Tim Meese

[Yuri]

Hello,

   The recent i.MX6 D/Q RM (IMX6DQRM, Rev. 3, 07/2015) clearly states in both tables,
that BOOT_CFG1[1:0] field defines  Row Address Cycles.

Table 5-9 (NAND Boot Fusemap)

Table 8-10 (NAND Boot eFUSE Descriptions)

http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6DQRM.pdf 

Regards,

Yuri.