iMX6 DDR3 Layout + Stress Test Tool

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iMX6 DDR3 Layout + Stress Test Tool

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GordyCarlson
NXP Employee
NXP Employee


Customer copied the schematic and code from the Freescale MCIMX6Q-SDB to design the Control Board for their product. They did not copy the PCB design / layout from the Freescale MCIMX6Q-SDB.


Instead of having 2 DDR3 SDRAM’s on the top side of the PCB and 2 DDR3 SDRAM’s on the bottom side of the PCB, they have all 4 of the DDR3 SDRAM’s on the top side of the PCB. They used the T-Topology to layout the address, command, and control lines for the DDR3 SDRAM’s.


The Freescale Hardware Development Guide for iMX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors recommends that you place 2 DDR3 SDRAM’s on the top side of the PCB and 2 DDR3 SDRAM’s on the bottom side of the PCB. Will the DDR3 calibration values generated by the Freescale DDR Stress Tester Program work correctly for the PCB design / layout approach that was used? That is, will they end up with a robust design or do we anticipate opportunities for problems with Control PCBA yield as they head into production?

 


-Gordy Carlson

Freescale FAE

Rochester, NY

 

 

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Gordon

DDR calibration algotithm will work OK

with chips placed on top side too. It is not

"linked" to specifc placement topology.

Best regards

chip

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Gordon

DDR calibration algotithm will work OK

with chips placed on top side too. It is not

"linked" to specifc placement topology.

Best regards

chip

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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