Hi,
iMX6SDL/DQ RM section 18.5.1.5.4 Clock Root Generator.
The figures in that chapter show the locations of the Clock Gates. The following signals show no gate (cg) in the figure, but they do have a gate according to the CCGRn registers:
Is this a documentation error, or does it mean these signals are really different than the others (maybe gated at a later stage)?
Solved! Go to Solution.
Hi Michel
correct description is given in CCGRn registers.
Best regards
chip
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Hi Michel
correct description is given in CCGRn registers.
Best regards
chip
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
So, just to confirm; the figures under section 18.5.1.5.4 Clock Root Generator should show (cg) for the PCIE, VD_AXI, CAN_CLK and UART signals? There is nothing "different" with the clock gating than any of the other signals, correct?
Yes, correct
Best regards
chip