Any follow up on this? Just ran into the same issue yesterday. I did include:
L2.6.35_10.12_EMI_FREQ_PATCH_UP/0001-ENGR00000000-Workaround-for-bus-freq-change.patch
The patch in the post above uses the same settings for all of the DDR2, this can also be accomplished in the profiles. Seems like this is an old issue that has not been addressed.
Derek
On my board the problem is caused by the line DRAM_REG[44] = 0x01020202; in the DDR2 133MHz definition in emi_settings.c
The value of 01 breaks the tWTR minimum timing requirement of 2 clocks or 7.5ns whichever is greater in the Micron datasheet for the DDR2 part I use.
Changing the value to 0x02020202 works for me.
Hope this helps some-one.
Clock switching saves 20% power for me and is well worth a look for idle periods.
Matt
Thank you for the patch. I can switch cpu frequencies through the sysfs interface on the fly now.
Regards
Oliver