Thanks Yuri,
I am glad we should be able to address the 256Mb Flash. We just want to make sure of the connections.
Our previous processor LPC3240 stated the following:
When using a system that implements 16-bit static memory, address signals A[23:1] are right-justified by one bit and output
on the physical address pins A[22:0]. Address signal A0 is not necessary because all transactions occur on half-word
boundaries. Address pin A23 is not used because the address space available for each CSn is 16 MB. This is done
automatically by hardware in the EMC controller when the value of MW is set to 0x1.
Therefore A23 was not valid and we connected A[22:0] to A[23:A1] on the flash (it has no A0 pin). We created our own A23 by using a second chip select line and connecting it through gated logic to A[24] on the flash.
Is A23 valid when addressing a 16 bit wide parallel NOR flash with the iMXRT1052? Can we use the following design or do we need to gate an additional chip select like SEMC_CSX[0] to pin A24?
SEMC_DA0 – A1
SEMC_DA1 – A2
SEMC_DA2 – A3
.
.
.
SEMC_DA14 – A15
SEMC_DA15 – A16
SEMC_ADDR0 – A17
SEMC_ADDR1 – A18
.
.
.
SEMC_ADDR6 – A23
SEMC_ADDR7 – A24 ??
SEMC_ADDR8 – CS5
