Ignoring the DMA initialization error the driver starts.
But the problem now is the TX clock. The RGMII_TX_CLK is connected to the TX clock output of the PHY. So both pins are acting as an output and driving against each other.
I used the same approach as for RMII and modified the part in imx93_set_intf_mode in dwmac-imx.c so the register 2C in GPR is set to 0. According to the manual TX_CLK of ENET QOS should now be an output. But measuring the signals at the pins shows that the i.MX93 is still driving against the output from the PHY.
So the question is, how can the TX_CLK pin be configured as an input for the TX clock signal for MII mode?