Dear Team,
We have observed that some power-down timing results do not meet the SoC's requirements. According to the specification, the power-down timing range must be between 0 and 10 ms. However, our measurement results did not meet this specification.
As far as I know, the power-down behavior will depend on the capacitor value and loading on the PCBA, which may explain why the timing range specified in the document cannot be met by all products. Would a failure in power-down timing have any impact on the product? Could we ignore the failures?
Here are the test results.
T1. Delay from PHY 1.2 V off to digital 2.5 V and 3.3 V off, the test results are -0.43ms~-0.3ms.
T3. Delay from NVCC_DRAM off to digital 1.8 V off, the test results are -0.18ms~-0.14ms.
T4. Delay from digital 1.8 V off to analog 1.8 V off, the test results are -0.31ms~-0.19ms.
T5. Delay from analog 1.8 V off to VDD_SOC off, the test results are -34.9us~-31.1us.
T9. Delay from VDD_SNVS_0P8 off to NVCC_SNVS_1P8 off, the test results are -3.97us~-2.53us.
Please provide recommendations.
