i.MX8MMini - SD/MMC IOMUX pin configuration possible error in REF manual

[vincentz63]

I wonder if there's an error in ref manual "i.MX 8M Mini Applications Processor Reference Manual, Rev. 2, 08/2019" regarding the ALT mode to connect some of the signals of the USDHC port to phyiscal pads.

I've tried to provide the exact references in the documentation to make it easier to review my question, and have hopefully managed to explain my reasoning clearly enough.

Page 805, table 6-22, lists the IOMUX pin configuration for the 3 USDHC ports states the following:

RESET_B | SD1_RESET_B.alt5 | SD2_RESET_B.alt5  | SD3_RESET_B.alt5

This implies that physical pad SD2_RESET_B connects to signal RESET_B of USDHC2 when its IOMUX register is set to mode ALT5.

Page 1254, table 8-1, states the following: "GPIO2_IO19 | SD2_RESET_B | ALT5".

This implies that physical pad SD2_RESET_B connects to signal IO19 of GPIO2 when its IOMUX register is set to mode ALT5. This is in direct contradiction with table 6-22.

Page 1264, table 8-1, states the following: "USDHC2_RESET_B | SD2_RESET_B | ALT0
                                                                                                        | GPIO1_IO08     | ALT5"

This implies that physical pad SD2_RESET_B connects to signal RESET_B of USDHC2 when SD2_RESET_B's IOMUX register is set to mode ALT0. This is in direct contradiction with table 6-22.

Page 1373, section 8.2.5.55 Pad Mux Register "IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B", states the following:

000 ALT0 — Select signal USDHC2_RESET_B
101 ALT5 — Select signal GPIO2_IO19

And that ALT5 is the default value.

This is in direct contradiction with table 6-22.

So given this, I'm intend on concluding that there is an error in table 6-22.

Except that I don't think the default value of IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B makes sense. Indeed, if the i.MX is to boot from USDHC2, then its signal RESET_B needs to be connected to pad SD2_RESET_B as no user software would have run to configure it.

So what ALT mode actuall connects SD2_RESET_B to USDHC2 RESET_B? And what is the default value of IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B?

I think the default value of IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B must connect SD2_RESET_B to USDHC2 signal RESET_B somehow (my understanding is that the i.MX relies on the default values of the IOMUX when booting, since no user software can run at this stage, only the boot ROM).

The same error appears to exist for other signals and all of the USDHC ports.

In addition, page 1262, table 8-1, states the following: "SRC_SYSTEM_RESET | SD2_RESET_B  | ALT6", but this configuration is not described in IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B. This also seems like an omission / error.

[radhikasomaiya]

Hi JP Arnaud,

Query : “So what ALT mode actually connects SD2_RESET_B to USDHC2 RESET_B? And what is the default value of IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B?”

Answer :

There is an understanding gap here about the IO muxing configuration for GPIO1_IO08 & SD2_RESET_B. Let me clear you. For each PAD there are up to 8 muxing options (called ALT modes). You can look into the below image for GPIO1_IO08 & SD2_RESET_B and its muxing options.

Name	Default	ALT0	ALT1	ALT2	ALT3	ALT4	ALT5
GPIO1_IO08	gpio1.IO[8]	gpio1.IO[8]	enet1.1588_EVENT0_IN				usdhc3.RESET_B
SD2_RESET_B	gpio1.IO[8]	usdhc2.RESET_B					gpio2.IO[19]

You can see in the table,

PAD - GPIO1_IO08: IOMUX register with ALT0 -> configures the pad as gpio1.IO[8]

IOMUX register with ALT5 -> configures the pad as usdhc2.RESET_B

Default value: gpio1.IO[8]

PAD - SD2_RESET_B: IOMUX register with ALT0 -> configures the pad as usdhc2.RESET_B

IOMUX register with ALT5 -> configures the pad as gpio2.IO[19]

Default value :  gpio1.IO[8]

Mapping :

Page 805, Table 6-22, lists the IOMUX pin configuration for the 3 USDHC ports :

RESET_B | SD1_RESET_B.alt5 | SD2_RESET_B.alt5 | SD3_RESET_B.alt5

This is the correct information according to the table mentioned above to set GPIO1_IO08.alt5 to provide a reset signal.

Page 1254, table 8-1, states : "GPIO2_IO19 | SD2_RESET_B | ALT5".

This implies that configure GPIO2_IO19 by setting muxing as SD2_RESET_B.alt5

Page 1264, table 8-1, states : "USDHC2_RESET_B | SD2_RESET_B | ALT0

| GPIO1_IO08 | ALT5"

This table reflects that to configure USDHC2_RESET_B signal you can either set muxing as SD2_RESET_B.alt0 or GPIO1_IO08.alt5 (Map this with the provided image above)

You can find this IOMUX configuration for pads in respective board schematic.

Query : “I think the default value of IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B must connect SD2_RESET_B to USDHC2 signal RESET_B somehow (my understanding is that the i.MX relies on the default values of the IOMUX when booting since no user software can run at this stage, only the boot ROM).”

Answer: You can set the iomux configuration inside the *.dts file to set the corresponding alternate modes for a pad. When you power on board it looks for the boot switches configuration, from where it can know from where to boot, and depending on that the configuration will be loaded from dts. This is a good article to understand the IOMUX handling in imx - https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/fsl%2Cimx-pinctrl.txt

Query : “page 1262, table 8-1, states the following: "SRC_SYSTEM_RESET | SD2_RESET_B  | ALT6", but this configuration is not described in IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B. This also seems like an omission / error.”

Answer: You can set pinctrl settings of usdhc2 for SYS_SYSTEM_RESET in dts by defining MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET same as you set for USDHC2_RESET_B & GPIO2_IO09.

You can check the information for mux registers into BSP (kernel_source/include/dt-bindings/pinctrl/pins-imx8mm.h).

Regards,

Radhika Somaiya