I have a question about the i.MX8M power-up sequence.In the spec “IMX8MDQLQCEC” on page 25，it said "Turn on... VDD_DRAM"，then "Turn on NVCC_XXX and NVCC_DRAM".When I researched the IMX8M demo design"MCIMX8M-EVK"，I have found "VDD_DRAM" is connected to the pin SW3A/B of PMIC(MC34PF4210A1ES)，"NVCC_DRAM" is connected to the pin SW2，according to the PMIC spec"PF4210" on page 17，I can see SW2 is powered before SW3A/B，so in the EVK design NVCC_DRAM is powered before VDD_DRAM？That does not match with the description in the spec “IMX8MDQLQCEC”，I cannot understand.
Hello,
PMIC MC34PF4210A1ES is used on the i.MX8M EVK. For the A1 case, according to
Table 8 (Startup configuration) SW2_SEQ is 6 and SW3_SEQ is 4. That is, "VDD_DRAM",
connected to SW3A/B，starts earler than "NVCC_DRAM", connected to SW2.
https://www.nxp.com/docs/en/data-sheet/PF4210.pdf
Have a great day,
Yuri
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Hello,
PMIC MC34PF4210A1ES is used on the i.MX8M EVK. For the A1 case, according to
Table 8 (Startup configuration) SW2_SEQ is 6 and SW3_SEQ is 4. That is, "VDD_DRAM",
connected to SW3A/B，starts earler than "NVCC_DRAM", connected to SW2.
https://www.nxp.com/docs/en/data-sheet/PF4210.pdf
Have a great day,
Yuri
------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer
button. Thank you!
