i.MX8M Mini decoupling capacitors recommendations

[lumen]

Hi,

In Table 14 of the IMX8M Mini Hardware Design Guide there are the decoupling capacitors recommendations described. In our design the voltages of the power domains are different to the EVK, e.x. NVCC_SAI2 is 3V3 instead of 1V8. Because of that we need to recalculate the decoupling capacitors of the power rails.

What are the requirements for each power domain (NVCC_JTAG, NVCC_SAI1, NVCC_SAI2,...)? Are there parameters like Ztarget available to calculate the decoupling capacitors?

Best Regards,

Patrick

[IvanRuiz]

Hello,

Generally, the Hardware Developer’s Guide decoupling capacitors recommendation in Table 10 is based on the EVK design. The exact number of capacitors on each rail (1.8V or 3.3V) depends on the number of balls connected to that rail, but there should be a cap (0.22uF) for every 1-2 balls,  and each ball should have a capacitor relatively close to it. Also, common for a group cap of 4.7 uF or 10uF may be applied.

Hope it helps!

BR,

Ivan.

[lumen]

Hi Ivan,

Thank you for your reply.

The recommendations in the HW design guide (EVK) for the net NVCC_NAND, NVCC_SAI1, NVCC_SAI3, NVCC_SAI5, NVCC_ECSPI, VCC_USB_3P3 is 5x220nF and 1x4.7uF. On the other hand for the net NVCC_JTAG, NVCC_SAI2, NVCC_GPIO1, NVCC_I2C, NVCC_UART, NVCC_SD1, NVCC_CLK only 3x220nF and 1x10uF is recommended. That means your rule of thumb unfurtunatly does not work. For us it is very important that the processor is working reliable over a wide temperature range (-40°C to +85°C).

For an Altera FPGA power design there is a tool available (see attachment) to make a PDN analysis to determine the decoupling capacitors. Is there a tool or a design guide available for the i.MX8M Mini to determine the decoupling capacitors?

Best Regards,

Patrick

[IvanRuiz · Accepted solution]

Hello,

As you mentioned this is a rule of thumb that the designers have been followed based on their experience since, otherwise, it will be necessary to know the intrinsic capacitance of the pin, the impedance of the routes in the layout, the intermediate layers, just to mention some involved in the analysis, which will make it very complicated to calculate. Unfortunately, there is no tool, but this rule of thumb that I have previously mentioned.

Thank you for your comprehension.

BR,

Ivan.