i.MX7d uSDHC CMD53 read error

[kadota]

When connecting a Silex SX-SDMAC to an i.MX7d uSDHC2 via SDR50 and running it, an error sometimes occurs when reading CMD53, and we are investigating the cause.
The tuning process does not use auto tuning, but instead sets STD_TUNING_EN in the uSDHC2_TUNING_CTRL register and EXECUTE_TUNING in the uSDHC2_AUTOCMD12_ERR_STATUS register, issues CMD19 40 times and waits for tuning to complete, but there was a post in the community below saying that when the default CMD and DATA[0] to DATA[3] are enabled in auto tuning, the Delay cell cannot be adjusted properly, and an error may occur when reading CMD53.
Even if auto tuning is not being performed, do I need to set only CMD and DATA[0] to be the target when tuning and perform tuning?

uSDHC auto tuning and possible SDIO failures - NXP Community

[Zhiming_Liu]

Hello,

The tuning process for the i.MX7d uSDHC2 should target only CMD and DATA[0] when performing tuning, even if auto tuning is not being used. This approach can help prevent errors when reading CMD53, especially when operating at higher speeds like SDR50.

Recommended setting: To address this issue, it's recommended to set TUNING_1bit_EN to use only the DATA0 line for auto-tuning. This should be sufficient, assuming that the PCB line lengths are well-matched with minimal skew between them.

Best Regards,
Zhiming

[kadota]

I understand that in the uSDHC2 tuning process, only CMD and DATA[0] must be set, even if auto-tuning is not used. Is it okay to set the uSDHC2_VEND_SPEC2 register to only target CMD and DATA[0] immediately before setting EXECUTE_TUNING in the uSDHC2_AUTOCMD12_ERR_STATUS register? Or are there any restrictions that require it to be set before any other register settings? Incidentally, when the CMD53 read error occurred this time, bit 15 (Reserved) of the uSDHC2_INT_STATUS register was set to 1. The manual says that 0 is always read out, but could you please tell me what this bit means?

[Zhiming_Liu]

Hello,

Is it okay to set the uSDHC2_VEND_SPEC2 register to only target CMD and DATA[0] immediately before setting EXECUTE_TUNING in the uSDHC2_AUTOCMD12_ERR_STATUS register? 

--> It is generally safe to set the uSDHC2_VEND_SPEC2 register immediately before setting EXECUTE_TUNING in the uSDHC2_AUTOCMD12_ERR_STATUS register. There are no specific restrictions requiring it to be set before other register settings.

Here's what the internal team responded to on a similar question:

The BSP default value for uSDHCx_VEND_SPEC2 means autotuning uses DATA[3:0]:

• TUNING_CMD_EN = 0
• TUNING_1bit_EN = 0
• TUNING_8bit_EN = 0

When SDIO interrupts are enabled, the async nature of the SDIO interrupts on DATA1 will confuse the auto tuning (it seems that the uSDHC module IP does not properlly comprehend SDIO DATA1 interrupts while autotuning is enabled on the 4 data lines).

Recommend setting TUNING_1bit_EN to use only DATA0 line for autotuning. This should be ok, since line lengths on PCB are well matched.

For bit 15 of  uSDHC2_INT_STATUS

-->

-->Or You can try to clear these bits to check if this issue can be resolved.

uSDHCx_AUTOCMD12_ERR_STATUS[SMP_CLK_SEL]
uSDHCx_MIX_CTRL[FBCLK_SEL]
uSDHCx_MIX_CTRL[AUTO_TUNE_EN]

Best Regards,
Zhiming

[kadota]

In the i.MX 7Dual Applications Processor Reference Manual, 10.3.8.13 Interrupt Status (uSDHCx_INT_STATUS) it says that bit 15 is Reserved (This read-only field is reserved and always has the value 0.), which is not what you answered, so I would like you to revise the Reference Manual or provide an errata. In addition, it seems that bit 15 is set when an error occurs, but how can I clear bit 15 when it is set?

>-->Or You can try to clear these bits to check if this issue can be resolved.
>uSDHCx_AUTOCMD12_ERR_STATUS[SMP_CLK_SEL]
>uSDHCx_MIX_CTRL[FBCLK_SEL]
>uSDHCx_MIX_CTRL[AUTO_TUNE_EN]
When should I clear these bits?
Is this just before setting EXECUTE_TUNING in the uSDHC2_AUTOCMD12_ERR_STATUS register?

[Zhiming_Liu · Accepted solution]

Hi

1. This is not any errata issue in RM. The description in the RM implies that the bit is not designed for use by customers, it's only reserved for internal debug. It's not that an error was generated because the bit was set, but that some error caused the bit to be set. So you can't fix this directly by clearing this bit. This bit is not the direct cause.

2. Normally set TUNING_1bit_EN to use only the DATA0 line for auto-tuning. This should be fine, all that is required is that the line lengths on the PCB are well matched. Suggest you troubleshoot the uSDHC line lengths in PCB design.

[kadota]

Thank you for your reply.

[kadota]

I understand that in the uSDHC2 tuning process, only CMD and DATA[0] must be set, even if auto-tuning is not used.
Is it okay to set the uSDHC2_VEND_SPEC2 register to only target CMD and DATA[0] immediately before setting EXECUTE_TUNING in the uSDHC2_AUTOCMD12_ERR_STATUS register?
Or are there any restrictions that require it to be set before any other register settings?
Incidentally, when the CMD53 read error occurred this time, bit 15 (Reserved) of the uSDHC2_INT_STATUS register was set to 1. The manual says that 0 is always read out, but could you please tell me what this bit means?

[kadota]

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