i.MX7D DDR3 Timing - Read/Write latency configuration for stability

[lehtor]

Hello,

I'm testing DDR3 configurations on a i.MX7D board due to random instability during heavy memory usage. This is related to my previous post here: https://community.nxp.com/t5/i-MX-Processors/i-MX7D-processor-sporadically-freezing-completely-when-...

We've come to the conclusion that the instability is caused somehow by heavy memory usage as reducing memory writes and reads in software running on the board causes the board to be much more stable (random freezing every 20-30min -> ~2h30min). We would like to test if changing the Read/Write latencies would make the freezing boards stable.

Our board has two MT41K256M16TW-107 IT:P memory chips with one chip select. I've tested running the board with only one memory chip in use by configuring the bus width to 16 instead of 32 and configuring the memory size as 500M in the bootloader. This configuration is stable on all boards with no freezing. I've also tried to raise the t_RFC timing from 260ns to 350ns and it made the freezing units more stable again with the full memory size (random freezing every ~2h30min -> ~5h20min). This seems to indicate that the problem lies in the memory timings somehow. We've run the i.MX 6/7 Family DDR Stress Test -tool and are using the calibration values it's giving out. Both the working boards and the randomly freezing boards give out the same calibration values.

I'm attaching both the register programming aid excel with our current configuration and the DDR3 documentation PDF for reference. Looking at the DDR3L-1866 Speed bins -page in the DDR3 documentation it seems to say that the -107 speed grade is backwards compatible with 3 different CL-values. I'm pretty sure this CL is the CAS read latency and the accompanying CWL is CAS write latency. How would one test these different values using the register programming aid excel? I found the WRITE_LATENCY and READ_LATENCY -fields (rows 114 and 115) in the excel, but in the notes it says that this field is automatically updated and is not recommended to be manually configured. Are these the same as the CL and CWL in the documentation? And if so should I change something else as well? And are there some other options I could try tweaking?

- Riku

[seb13]

Hi Lehtor,

We're experiencing a similar issue on our i.MX7D board with the same RAM (MT41K256M16TW-107 IT:P). Have you identified the root cause and found a solution?

Kind regards

[AldoG]

Hello,

Your understanding is correct, but please note that the WL and RL are updated automatically from setting provided in the "Device Information" table or other cells, and should not be changed manually. We also strongly advise customer do not modify latency parameters on their own.

Best regards/Saludos,
Aldo.

[lehtor]

Hi,

I'm well aware that the fields are not supposed to be edited and mentioned the comment in the excel which states the same. The fields themselves only check if the memory is either DDR3, LPDDR3 or LPDDR2, which seems to indicate the set values are more like defaults than actual computed values.

My main concern with the fields is that if the sheet has other fields which don't reference these two fields in some more complicated formula that has these same kinds of assumptions about the write and read latencies, and would also need editing.

I do appreciate the concern and understand that these are not supposed to be changed, but not changing anything won't solve the stability problem. I will still have to try and fix the issue, and with instructions or any guidance at all it will most likely go more smoothly. Also if there are some other parameters I could and/or should try to change for a more stable system I'm more than willing to let the write/read latencies be as is, I don't have any specific need to fiddle with these two parameters if the problem can be solved with changing some other parameter.