i.MX6SoloX RGMII TX_CTL delay

[vadimaleynikov]

Hello.

In i.MX6SoloX RGMII1_TX_CTL delay to AR8035  it is recommended to implement 1.75ns TX_CTL delay as PCB trace delay and the following NXP PCB photo is presented as an example:

But the reference for the SABRE Board (https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Fproducts%2Fmicrocontroll... isn't contain data.

The RGMII2 TX traces in the LAY-27962_C.brd have  the following lengths:

RGMII2_TXCLK: 1762.4mil

RGMII_TXD3: 2068.05mil

RGMII2_TXD2: 1899.02mil

RGMII2_TX1: 1835.57mil

RGMII2_TXD0: 1778.63mil

RGMII2_TXEN: 1710.34mil.

So actually the TXCLK is almost shortest trace in the RGMII2 TX group and no delay is implemented by the PCB clock trace.

How the recommended RGMII clock delays are implemented in the NXP reference boards/design?

Best regards,

Vadim Aleynikov

[Yuri]

Hello,

Two fields RXC_DLY and TXC_DLY  of ENETx_ECR register  were added

in the recent i.MX6SX RM. 

Regards,

Yuri.

[vadimaleynikov]

Hello,

Thank you for the message. Do you mean RM Rev. 1, 6/2016? If these bits really control anything? What are values of these delays? The i.MX6SX datasheets don't contain these data.

Best regards,
Vadim

[Yuri]

Hello,

  Appears,  i.MX6SX doesn't have that feature (RXC_DLY and TXC_DLY  of ENETx_ECR register).

Regards,

Yuri.

[Yuri]

Hello,

The issue is under discussion yet : https://community.nxp.com/thread/435696 

Regards,

Yuri.

[igorpadykov]

Hi Vadim

reference designs are made when not all chip parameters are fully

validated and formally it is necessary to follow delays given in

Table 69. RGMII Signal Switching Specifications i.MX6SX Datasheet

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SXCEC.pdf

Best regards
igor
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