i.MX6Q/DL 4GB DDR3 RAM porting

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i.MX6Q/DL 4GB DDR3 RAM porting

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ezerochiou
Contributor III

Dears,

We'd like to design a customized board which support 4GB DDR3 RAM.

We had ever found Linux BSP 4.1.0, but it seems only 1GB and 2GB DDR3 codes we can refer .

Is there any reference Freescale evaluation boards in Linux BSP 4.1.0 or Yocto project we can reference? ex: we refer sabre-lite codes to develop 2GB DDR3 bsp.

Any ideas we can start to do if there is no 4GB DDR3 reference codes?

Thanks a lot.

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ezerochiou
Contributor III

Dear Chip,

Sorry for my misunderstanding.

BRs,

Ezero

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igorpadykov
NXP Employee
NXP Employee

Hi Ezero

please look at attached 4GB script.

Best regards

chip

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

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ezerochiou
Contributor III

Hi Chipexpert,

  • Did the file you attached be exported by "i.Mx6DQSDL DDR3 Script Aid" and I can apply the result according to the DDR3 RAM chip datasheet on flash_header.S by myself ? In my understanding, it's a H/W initial level.  Am I right?

  • Except flash_header.S. Do I need to modify U-boot and kernel codes?

For example:

[uboot]

dram_init()

{

...

gd->bd->bi_dram[0].size =.............;

}

[kernel]

./arch/arm/mach-mx6/board-mx6q_sabresd.c

mx6q_sabresd_reserve() {

...

phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size, SZ_4K, 4u * 1024 * 1024 * 1024);

...

}

  • In your experience. How much size of 4GB DDR3 RAM will be recognized by Linux (Kernel 3.0.35 or 3.10.17)

Thanks  a lot.

chipexpert 留言:

Hi Ezero

please look at attached 4GB script.

Best regards

chip

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

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igorpadykov
NXP Employee
NXP Employee

Hi Ezero

4GB vs 2GB DDR3 codes changes are minimal, you can compare

settings in flash_header.S.

For  memory (and other changes) one can look at

i.MX_6Dual6Quad_BSP_Porting_Guide.pdf

L3.0.35_4.1.0_LINUX_DOCS

In uboot this will be in uboot/include/configs/board_xx.h.

Linux will see max. 3840MB as shown on sect.2.3 "DDR mapping to

MMDC controller ports" IMX6DQRM

Best regards

chip

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ezerochiou
Contributor III

Hi Chip,

Which flash_header.S can I compare? As I known "mx6q_arm2/flash_header.S", "mx6q_hdmidongle/flash_header.S" and "mx6q_sabreauto/flash_header.S" are 2GB settings. But I can't find similar 4GB RAM settings in u-boot.

./rpm/BUILD/u-boot-2009.08/board/freescale/mx6sl_arm2/flash_header.S

./rpm/BUILD/u-boot-2009.08/board/freescale/mx6q_sabreauto/flash_header.S

./rpm/BUILD/u-boot-2009.08/board/freescale/mx6q_hdmidongle/flash_header.S

./rpm/BUILD/u-boot-2009.08/board/freescale/mx6q_sabresd/flash_header.S

./rpm/BUILD/u-boot-2009.08/board/freescale/mx6q_arm2/flash_header.S

./rpm/BUILD/u-boot-2009.08/board/freescale/mx6q_sabrelite/flash_header.S

./rpm/BUILD/u-boot-2009.08/board/freescale/mx6sl_evk/flash_header.S

Thanks.

chipexpert 留言:

Hi Ezero

4GB vs 2GB DDR3 codes changes are minimal, you can compare

settings in flash_header.S.

For  memory (and other changes) one can look at

i.MX_6Dual6Quad_BSP_Porting_Guide.pdf

L3.0.35_4.1.0_LINUX_DOCS

In uboot this will be in uboot/include/configs/board_xx.h.

Linux will see max. 3840MB as shown on sect.2.3 "DDR mapping to

MMDC controller ports" IMX6DQRM

Best regards

chip

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igorpadykov
NXP Employee
NXP Employee

Hi Ezero

I meant flash_header.S which you found with file which I sent.

Best regards

chip

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ezerochiou
Contributor III

Hi Chip,

I saw a file "MX61Q_4GB.inc.zip" in your reply on AUG/31. And I could connect to the links "L3.0.35_4.1.0_LINUX_DOCS" and " IMX6DQRM" replied by you on SEP 2.

But, I didn't see flash_header.S you sent.

I lost reply from you?

Thanks a lot.

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igorpadykov
NXP Employee
NXP Employee

Hi Ezero

I did not send flash_header.S.

I attached MX61Q_4GB.inc.zip" only

and suggest you to compare them (preferably with"mx6q_arm2/flash_header.S"

though it is not important) yourself.

Best regards

chip

4,233 Views
ezerochiou
Contributor III

Dear Chip,

Unfortunately, we got error when we try to use DDR stress tester on 4GB ram board.

Here is the log:

DDR stress tester v1.0.2 with i.MX6Q error

Total memory is 4G bytes, 8G bits Dual Die (2CS) * 4.

Detail log as attachments.

------------------------------------------------------------------

Would you like to run the write leveling calibration? (y/n)

  Please enter the MR1 value on the initilization script

  This will be re-programmed into MR1 after write leveling calibration

  Enter as a 4-digit HEX value, example 0004, then hit enter

0000 You have entered: 0x0000

Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x000D000B

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x0012000D

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00040012

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x017E000F

Would you like to run the DQS gating, read/write delay calibration? (y/n)

Starting DQS gating calibration...

. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

------------------------------------------------------------------

Would you like to run the write leveling calibration? (y/n)

  Please enter the MR1 value on the initilization script

  This will be re-programmed into MR1 after write leveling calibration

  Enter as a 4-digit HEX value, example 0004, then hit enter

0004 You have entered: 0x0004

Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x000E0006

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00150010

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00040016

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x017F000F

Would you like to run the DQS gating, read/write delay calibration? (y/n)

Starting DQS gating calibration...

. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!

Could you please help us to review our script aid?

Thanks a lot.

BRs,

Ezero

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mrleo
Contributor IV

Hi Ezero,

Before I use 4G bits (1CS) *4,total memory is 2G bytes is ok for me.

Now my board total memory is 4G bytes, 4G bits (2CS) *8.

I have met the same problem with you.

Have you solve your issues?

Could you give me some advices?

Thanks,

Leo

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igorpadykov
NXP Employee
NXP Employee

Hi Ezero

I would suggest to check carefully below link document,

in script for example tFAW is incorrect (should be 0x1F, if you read

attached datasheet https://community.freescale.com/servlet/JiveServlet/download/438061-281103/99H02-11185D.pdf

p.17, tFAW=32nCK for 2KB page)

"0xB8BE7955    // MMDC0_MDCFG0"

MX6 DRAM Port Application Guide-DDR3 link

https://community.freescale.com/docs/DOC-101708

However even with wrong values it is strange that it:

"dram test fails for all values."

This may point that smth severely wrong with hardware:

broken/missed/interchanged data/address lines e.t.c.

You can just run SDK simple ram test with jtag, testing signals

with oscilloscope. With low frequencies (about 200MHz) it should run

fine with reference board settings (*.inc files in tools/rvd folder).

Best regards

igor

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ezerochiou
Contributor III

Dear Chip,

Sorry for my misunderstanding.

BRs,

Ezero

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