i.MX6DualLite PCIe bus clock question

cancel
Showing results for 
Search instead for 
Did you mean: 

i.MX6DualLite PCIe bus clock question

447 Views
kostagodin
Contributor I

Hi,

A standard implementation of PCIe on i.mx6 is using IMX6QDL_CLK_SATA_REF_100M to drive ref_100m and pcie_bus clocks (the later via LVDS1) but i.MX6DualLite RM does not mention SATA clock - for example it is not available for LVDS source selection in CCM_ANALOG_MISC1 register on page 917. i.MX6Dual RM describes this clock but it seems to be removed from i.MX6DualLite RM, probably because DualLite does not support SATA.

Is it still possible to use this SATA clock on i.MX6DualLite for PCIe?

Regards,

Kosta

Labels (2)
Tags (2)
0 Kudos
4 Replies

100 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Kosta

you are right, this clock is not available according to RM. Note that

HW Design Checking List for i.Mx6DQSDL Rev2.8.xlsx

HW Design Checking List for i.MX6DQSDL  recommends:

PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip

can't pass PCIe Gen2 compliance test.. Recommend using external PCIe 2.0/3.0

clock generator..

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

0 Kudos

100 Views
kostagodin
Contributor I

Hi Igor ,

But Linux pci driver (pci/host/pci-imx6.c) contradicts DualLite RM because it stills expects ref_100m (SATA) clock for all non i.MX6SX devices. It even has a comment /* sata_ref is not used by pcie on imx6sx */ but Daul Lite is not SX because it defines pci in device tree as "fsl,imx6q-pcie" via included imx6qdl.dtsi. Either the driver or RM must be changed to match (probably the problem is that DualLite and SX RM is unified?). We have only i.MX6Q Sabre boards here but want to move to DualLite in the final product hence the question. If any Sabre DualLite board has operational pci than the problem is definitely in RM.

And about the CLKx: yes, we are planning to use external pcie_bus clock and as I understand it will need to go into PLL6 (ENET) via bypass. Is there any Sabre board that does it? I am curious to see device tree of this configuration.

Regards,

Kosta

0 Kudos

100 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Kosta

attached pci-imx6.c from L3.10.17, it does not mention i.MX6SX,

still it is expected that sata_ref is not available for all devices.

~igor

0 Kudos

100 Views
kostagodin
Contributor I

Hi Igor,

We are using pci-imx6.c provided in Freescale 3.14 Linux distro - it has Freescale copyright and does mention i.MX6SX at line 323 (see attached).

* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.

...

if (is_imx6sx_pcie(imx6_pcie)) {

   ...

} else {

   ...

   /* sata_ref is not used by pcie on imx6sx */

   ret = clk_prepare_enable(imx6_pcie->ref_100m);

   ...

Regards,

Kosta

0 Kudos