i.MX6DQP Power-Down sequence.

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i.MX6DQP Power-Down sequence.

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Contributor III

Hello community,

I have one question about Power-Down sequence for i.MX6DQP.

In Datasheet of i.MX 6DualPlus/6QuadPlus, IMX6DQPAEC rev 3, 11/2018,

Section 4.2.2 Power-Down Sequence say that 

   "There are no special restrictions for i.MX 6DualPlus/6QuadPlus SoC."

Is this applied only Supplies Contact in Table 95 ?

Or all contact both "Supplies Contact in Table 95." and "Functional Contact in Table 96." ?

Best regards,

Ishii.

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NXP TechSupport
NXP TechSupport

Hello,

  The power down requirements concern only power supply pins (mentioned in the Table 95).
All  I/O pins must not be externally driven while the I/O power supply for the pin (NVCC_xxx)

is OFF. This can cause internal latch-up and malfunctions due to reverse current flows.

Regards,

Yuri.

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NXP TechSupport
NXP TechSupport

Hello,

  The power down requirements concern only power supply pins (mentioned in the Table 95).
All  I/O pins must not be externally driven while the I/O power supply for the pin (NVCC_xxx)

is OFF. This can cause internal latch-up and malfunctions due to reverse current flows.

Regards,

Yuri.

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Contributor III

Hello Yuri,

Thank you for your quick response.

Does it have some constraint between external drive off and I/O power supply off timing?

i.e. External driver must off faster than I/O power supply befor xx [ns].

Or is it OK to off at same time?

Best regards,

Ishii.

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NXP TechSupport
NXP TechSupport

Hello,

   Really there are no strict timing restrictions regarding  external drive off and I/O

power supply off. So, the same time for the powers switching off is OK.

Regards,

Yuri.

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Contributor III

Hello Yuri,

Thank you for your suggestion.

I will ask it to my customer.

Best regards,

Ishii.

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