i.MX6 ULL powerdown sequence

[ban45]

Tell me more about why you have to follow the power-down sequence.
Tell us more about what's happening on your device.
Do I need to protect it for software termination?
Will it be damaged by the backflow of voltage in the device?

[Yuri]

@ban45 

Hello,

   the issue has been mainly discussed in

https://community.nxp.com/t5/i-MX-Processors/Power-Down-Sequence-i-MX6ULL/td-p/1159053

   Incorrect power down sequence may affect i.MX6 lifetime.

    Generally it is possible to turn off the power at the same time, assuming the i.MX6 SRTC
is not used. I do not think, that the i.MX6 lifetime will be affected significantly in such case.

  Nevertheless, to be fully on safe side - recommended power up / down sequence should be
followed.

[ban45]

Hi

I would like to know what happens if VDD_SOC_IN and VDD_HIGH_IN are swapped.
Is it okay to drop A and B at the same time?
It is said that the life will be shortened. Please tell me the reason for the shortening.

[Yuri]

@ban45 
Hello,

   i.MX 6ULL is i.MX 6UL derivative. IMX 6UL till rev. 1.2 has the following issue:
SNVS_LP registers may be reset during system power down or power up.
The i.MX 6ULL is not affected, but the requirement VDD_HIGH_IN power down
is earlier than VDD_SOC_IN concerns the erratum.
  In general, from the Datasheet: 
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst-case scenario)

Regards,
Yuri.

[ban45]

Hello

It was not mentioned in Chip Errata for the i.MX 6ULL.

But,There was a description in Chip Errata for the i.MX 6UltraLite.

Can I refer to Chip Errata for the i.MX 6UltraLite and use the  i.MX 6ULL?

There was the following description(Errata for the i.MX 6UltraLite).

• VDD_HIGH_IN power down is earlier than VDD_SOC_IN.
• VDD_HIGH_IN voltage power is less than or equal to 3.0 V.)

Does this mean that the power down sequence sets VDD_HIGH_IN to less than 3.0V before the VDD_SOC voltage drop?
Is it necessary to reduce VDD_HIGH_IN to 0V?

Isn't the PMIC configurable time of 2ms irrelevant?

[Yuri]

@ban45 
Hello,

    I mentioned the i.MX 6UL erratum just to explain why the restriction regarding voltage's
up / down sequence takes place. The i.MX 6UL erratum is not actual for i.MX 6ULL,
but power up /down sequence - does.

Regards,
Yuri.

[ban45 · Accepted solution]

Hello

Is time irrelevant if the order of VDD_SOC_IN and VDD_HIGH_IN is followed?
What is the voltage that VDD_SOC_IN and VDD_HIGH_IN must hold?

[Yuri]

@ban45 
Hello,

     Yes, in some sense timings are  irrelevant, assuming reasonable boot timings.
The voltage specs may be found in the i.MX 6ULL Datasheet(s).

Regards,
Yuri.

[ban45]

Hi

Should I keep the following voltage range in the fall sequence?

VDD_SOC_IN  is  1.325V

VDD_HIGH_IN is 2.8V

Is it okay？ VDD_HIGH_IN is higher than 2.8V when VDD_SOC_IN is 1.325V or less.

Regards,

[Yuri]

@ban45 
Hello,

  During normal operations power supply voltages should be in range,
specified in "Operating Ranges" table of i.Mx 6ULL DataSheet.
VDD_SOC_IN of 1.325V and VDD_HIGH_IN of 2.8V satisfy specs.
   During power-down the voltages will decrease. 

Regards,
Yuri.

[ban45]

Hello

Suppose the SNVS power is off in the power down sequence
Do I need to maintain the order of VDD_SOC_IN and VDD_HIGH_IN? In the data sheet, it seems to affect the registers held by the SNVS power supply. Isn't the order affected if the SNVS power is off?

Regards

[Yuri]

@ban45 
Hello,

Let me emphasize two points.

1.
  To be fully on safe side - for applications, where highest reliability
is the most important - power up/down sequence requirements must be satisfied.

2.
   In general - for consumer application - it is possible to turn off the power at the same time.

Regards,
Yuri.

[ban45]

Hello

>2.
>   In general - for consumer application - it is possible to turn off the power at the same time.

How much timing shift can I tolerate if the power is turned off at the same time (VDD_SOC_IN, VDD_HIGH_IN)?
It may shift due to the decoupling capacitor and current consumption.
How many milliseconds can the deviation be tolerated?
In the event of a power outage, the power will be turned off.
SNVS is a power source from the PMIC.
In that case, is it okay to think that the power is turned off at the same time?
The application used will be a consumer product.

Best regard.

[Yuri]

@ban45 
Hello,

   Yes, at the event of a power outage, the power will be turned off,
and this case we can considered that the power is turned off at the same time. 

Regards,
Yuri.

[ban45]

Hi

Could you tell me the difference between highest reliability and Consummer? I am using MCIMX6Y2CVM08AB.
I thought it was a consumer  because it was a consumer product.
Is it right?

best regard.

[Yuri]

@ban45 
Hello,

   requirements regarding safety and reliability are application dependent,
and devices used in design should meet corresponding requirements.

https://www.nxp.com/company/our-company/quality/product-qualification:QUALITY__QUALIF

Regards,
Yuri.

[ban45]

Hi

I would like to ask about the points you answered .

  >In general - for consumer application - it is possible to turn off the power at the same time.

What kind of consumer application can be considered?
Is it for factories or homes?
Could you tell me.

We consider space and aviation to be highly accurate.
Would you please teach me how to divide it?

best regard

[Yuri]

@ban45 
Hello,

  When designing, engineers must analyze their system: what occurs in case of unexpected crash (software, or power off).  Is such situation dangerous for people and other systems? Consumer applications do not require very strong conditions here.

Regards,
Yuri.