i.MX6. RMII + RGMII.

[EgleTeam]

Hi,

1. Does it possible to make it work 2 ethernet ports ( RMII + RGMII) at the same time on i.MX6?. Now we only use RMII (CLK on GPIO16).

2. Is it supported by mainline or non-mainline Linux kernels?. What versions?

Best Regards,

Manuel.

[igorpadykov]

Hi Egle

not, it is not possible to use both RMII + RGMII at the same time.

Best regards

igor

[EgleTeam]

Thanks Igor,

BTW, I was wrong: we use RGMII_TX_CTL (GPIO16 is not available) so 1 pin is common and 100% not possible in our case. If GPIO16 is used instead of RGMII_TX_CTL: what is the reason to don't be possible if there are no pins shared?

Regards,

Manuel.

[sinanakman]

Hi EgleTeam

Before Igor gives a definitive answer, I suggest to take a look at the ENET_RCR[RGMII_EN]

description. There is a note there :

NOTE: Do not set both RCR[RGMII_EN] or RCR[RMII_MODE].

I assume enabling both RMII and RGMII is not supported at all and

probably RGMII would override as there is only one controller per Rx and Tx.

Hope this helps

Sinan Akman

[igorpadykov · Accepted solution]

Hi Sinan

yes, it is correct there is only one ethernet controller so

it can not work simultaneously with both RMII and RGMII interfaces.

Processor on LWN net link will have two independent gigabit ethernet controllers,

however it is quite different from i.MX6S and other i.MX6 processors.

~igor

[hariharan_m]

Hi,

What is the difference in IMX6S? Is it support both RMII and RGMII at the same time?

[sinanakman]

Hi Igor, thanks for your response. It was actually Egle Team wanted to know about the SoC.

I am well aware of the new SoC details. Thanks for your follow up.

Regards

Sinan Akman

[EgleTeam]

Thanks Sinan,

Now I got it: separate pins for RGMII and RMII modes but only one controller at hardware level. Sounds a bit strange but for sure it must to have a good reason.

Time ago I read that Freescale plans to launch an i.MX6 revision with 2 x RGMII plus 2 x Cortex M4 cores (I guess for real time like TI Sitara family): we will wait until then.

Thanks a lot to both!

Manuel.

[sinanakman]

Hi EgleTeam

There is some public information related to that :

http://lwn.net/Articles/598434/

AFAIK, the reference manuals are only available under NDA at this

point but if you like to consider a new design based on this SoC

please speak with your FAE and I am sure Freescale will be happy to

discuss SoC's details.

Regards

Sinan Akman

[EgleTeam]

Nice Sinan!,

I can see interesting things: more pwm, adc, qspi, more usb otg, 2 rgmii. I'm willing to bet that this IC won't be pin-to-pin compatible with the previous versions and perhaps only available in "solo" version, i.e.: direct competition with new Sitara Cortex A9 (but for sure much more cheaper).

Thanks for the advice, on any case we will wait because it is also expected to see new i.MX7 and i.MX8 on next year. We don't have enough resources to develop many SoC boards at the same time so sometimes we need to choose.

Regards,

Manuel.