i.MX6 PCIe RX FIFO Full?

[massohy]

Hello,

I have a trouble at PCIe between i.MX6 and Altera FPGA.

There is used yocto Linux as OS. I allocated memory space by pci_alloc_consistent() on device driver, FPGA write data to physical address of its memory.

At first, it was well. But if I transferred continuously, then i.MX6 cannot receive soon, RX FIFO full signal from i.MX6 asserted after it. I watched this behavior by Altera Signal Tap.

I am confused because PCIe RX of i.MX6 become full in spite of transfer rate is bery slow (about 1MB/s).

I am thinking that because FPGA write to memory directly, software (include device driver, OS) didn't relate it.

1. i) Please tell me this recognition is correct or not. If it is correct, then I will focus to fix FPGA.

1. ii) How do you think why does RX FIFO become full?

[igorpadykov]

Hi mas

for improving i.MX6 PCIe performance one can try to use

IPU as the bus master(DMA), using patches on

i.MX6Q PCIe EP/RC Validation System 

For narrow down issue may be helpful try baremetal sdk test

(sdk zip can be found on https://community.nxp.com/thread/432859 )

Best regards
igor
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[massohy]

Hello igor,

Thank you for your reply and induction.

It is great solution to use IPU as DMA. I

I will be grateful if you could advise to my question.

• Should I patch for my kernel whether I use or not IPU as DMA?
• Can I apply this solution for my environment that CPU of i.MX6 don't execute read command? Or if FPGA perform burst write to physical memory, then is it same effect that i.MX6 read from FPGA by DMA(IPU)?
• If I don’t use DMA, does rx fifo of PCIe in i.MX6 become full frequently?

And thank you for introduce SDK. Because Mentor discontinue to supply Code Sourcery Lite for ARM, I used ARM arm-none-eabi-gcc, but I have not succeeded to build SDK.