i.MX6 ECSPI slave: Maximal SCLK frequency (fast / slow group)

[elibil]

Hello,

I'm trying to figure out the maximal ECSPI frequency as slave in read mode on an i.MX6 device. According to the datasheet [1] (section 4.11.2.2), the max frequency depends on whether the relevant pin is in the fast or slow group, and the footnotes outline which is which.

But I suspect that the list given in section 4.11.2.2 (slave timing) is wrong. Here's why:

Let's look at section 4.11.2.1 of the datasheet, which gives the timing for master mode. The ECSPI pins listed there in footnotes 1 and 2 are candidates for MISO pads, which makes sense: The data rate depends on whether the data input pad is in "slow" or "fast" group (whatever that means).

When switching to slave mode, the MISO and MOSI pins swap directions, so I would expect other pins (i.e. the MOSI candidates) to be enlisted in the footnotes to the timing spec for slave mode. But they are the same pins as in master mode. So according to 4.11.2.2, the maximal frequency for reading depends on the choice of the data output pins, which makes no sense.

Specifically, I'm going to use EIM_D22 as MISO and EIM_D28 as MOSI. According to footnote 2 of Table 52, EIM_D22 is listed as a fast pin, so I should be allowed to run at 25 MHz (40 ns). But again, it doesn't make sense to me that this decision depends on EIM_D22 = MISO, which functions as an output from the i.MX6 device in slave mode.

Insights are highly welcome.

Regards,
   Eli

[1] https://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

[art · Accepted solution]

Actually, the Table 52 is correct sice on the SPI bus the Read and Write cycles are defined from the current bus Master's point of view. So, when the i.MX6 eCSPI module operates as a Slave, an external Master reads data from it, so, eCSPI outputs data to an external Master. From this point of view, the definitions of the Table 52 are correct.

Have a great day,
Artur

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[elibil]

A big thanks for that one!

Now, when I look at table 52, I realize that the propagation delays, which also depend on the slow/fast grouping, relate to the MISO. A 25 ns propagation delay (on the slow group) on MISO indeed matches the idea of a slow read cycle performed by an external master.

But this means something even sweeter: In slave mode, data can go into the i.MX6 device with a 66 MHz clock (the external master writes the data, and the datasheet says 15 ns), which happens to be important in my project.

Did I get it right?

Regards,

    Eli

[art]

Yes, you understand it right.

Best Regards,

Artur

[elibil]

Great! Thanks.

[fabio_estevam]

Hi Eli,

Just wanted to let you know that i.MX SPI Slave series has been posted recently:

https://www.spinics.net/lists/arm-kernel/msg586465.html 

,in case you want to try it.

Regards,

Fabio Estevam

[elibil]

Thanks. I'm aware of that patch.

The thing is that I'm not in control of the kernel version, and it's 4.1. So applying it as with probably requires applying everything until that point (more or less...?) and who knows if I haven't broken something because I failed to patch some other file with some mutual dependency.

But I'll definitely learn from this patch.

Regards,

    Eli