i.MX502 IOMUX for NOR Flash boot

[norishinozaki]

Hello,

I'm configuring NOR Flash as boot device by looking at Table 6-9 in RM below.

Does this instruct that,  for NOR Flash boot, the Flash pins must be connected to the Pads specified in this table?

Then ROM code configures the IOMUXes the Pads without setting correspondent GPIO pins?

Does this sentence mean that we need to the configure shadowed pins by GPIO to be assingned propery to the specified Pad at reset?

However we don't need to configure manually for non-shadowed pins because ROM code does that.

We only need to conigure shadowed pins by GPIO.

Is this correct?

Best regards,

Nori Shinozaki

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[igorpadykov]

Hi Nori

yes it is correct, for NOR Flash boot the flash pins must be connected to

the pads specified in this table. Also non-shadowed pins are

set by ROM code, no need to additionally configure them.

Best regards

igor

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[norishinozaki]

Thanks Igor,

Now please explain how to configure shadowed EIM_D[0] to EPDC_D0.ALT2 as shown in the table when it's reset for NOR boot.

When I look at the IOMUXC register for EPDC_D0, the default value for MUX_MODE is 0001(GPIO[0]).

How can I set 010 for EIM_D[0]?

Also I have to set the SELECT_INPUT register to mode ALT2.

How can I do that?

Best regards,

Nori Shinozaki

[igorpadykov]

Nori,

there is no need for configuration of EIM_D[0]  EPDC_D0.ALT2

since NOR boot is performed on D16-D31 pads (selection

BOOT_CFG2[7:6]=01 - Not Muxed, 16-bit data (high half) interface)

EIM_DA0-15.ALT0 are for selection BOOT_CFG2[7:6]=00 - Muxed, 16-bit data (low half) interface

Shadowed pads are not used for boot.

Best regards

igor

[norishinozaki]

Hello Igor,

Thanks again,

Let me confirm the Table 23-2 below

Is these correction in red are correct?

Because...

BOOT_CFG2[7:6]=00 - Muxed, 16-bit data (low half:DA0-15) interface

From 23.101.1 EIM_CSGCR1,

     MUM=1

     DSZ=001(lower 2bits applied)

So EIM_BOOT=0x101

BOOT_CFG2[7:6]=01 - Not Muxed, 16-bit data (high half:D16-31) interface

From 23.101.1 EIM_CSGCR1,

     MUM=0

     DSZ=010(lower 2bits applied)

So EIM_BOOT=0x010

Best regards,

Nori Shinozaki

[igorpadykov]

Hello Nori,

it is not necessary to use 23.101.1 EIM_CSGCR1

since iROM changes these settings as described in i.MX50 RM Boot Chapter:

NOR boot is performed on D16-D31 pads (selection

BOOT_CFG2[7:6]=01 - Not Muxed, 16-bit data (high half) interface)

EIM_DA0-15.ALT0 are for selection BOOT_CFG2[7:6]=00 - Muxed, 16-bit data (low half) interface

Shadowed pads are not used for boot. This corresponds to:

EIM_CS0GCR1[MUM] = ~BOOT_CFG2[6];

DSZ[0] = EIM_CS0GCR1[16] = ~ (BOOT_CFG2[7] | BOOT_CFG2[6]);

~igor

[norishinozaki]

Hello Igor,

Thank you!

You mean DSZ[1] isn't cared, right?

Then, EIM_BOOT can be either of following values.

#Not muxed: BOOT_CFG2[7:6] = 0x01

EIM_BOOT[2:0] = 0x000

2: MUM    = 0

1:DSZ[1] = *(say, 0)

0:DSZ[0] = 0

#Muxed: BOOT_CFG2[7:6] = 0x00

EIM_BOOT[2:0] = 0x101

2: MUM    = 1

1: DSZ[1] = *(say, 0)

0: DSZ[0] = 1

So, as long as we use Not Muxed, 16-bit data (high half) settings, we don't neet to care about the 23.101.1 EIM_CSGCR1 register. Because ROM will set it so.

In other words, we can use Muxed mode by settings EIM_BOOT[2:0] pins in 0x101.

Best regards,

Nori Shinozaki

[igorpadykov]

Hello Nori,

yes, ROM sets EIM_CSGCR1 register

BOOT_CFG2[7:6]=00 - Muxed, 16-bit data (low half) interface  =>  DSZ = 001

BOOT_CFG2[7:6]=01 - Not Muxed, 16-bit data (high half) interface) =>DSZ = 010

DSZ[1] =~ (~(BOOT_CFG2[7] ^ BOOT_CFG2[6]);

~igor

[norishinozaki]

Hello Igor,

Thanks but you wanted to write

DSZ[1] =~ (~BOOT_CFG2[7] ^ BOOT_CFG2[6]);

?

Now it tuned out my customer has to use D0-15 pins to connect NOR FLASH for booting.

They need to set BOOT_CFG2[7:6]=00 by GPIO Boot Overrides as written in the Table 6-8 below

Then when I look at Table 6-3 to try to find out the GPIO pins but there are no "Contact" for BOOT_CFG2[7:6].

How can we really set BOOT_CFG2[7:6]=00?

BTW, EIM_BOOT[2:0] are internal signals generated by BOOT_CFG2[7:6]?

Best regards,

Nori Shinozaki

[igorpadykov]

Hello Nori,

yes EIM_BOOT are internal signals generated by BOOT_CFG2[7:6]:

EIM_DA14  BOOT_CFG2[6]

EIM_DA15  BOOT_CFG2[7]

~igor

.

[norishinozaki]

Hello Igor,

Thanks, so the only things they need to do non-mux NOR boot,

Tie EIM_DA14 and 15 to low when reset.

Is this correct?

Nori Shinozaki

[igorpadykov]

Hello Nori,

BOOT_CFG2[7:6]=01 - Not Muxed, 16-bit data (high half) interface)

EIM_DA14 = BOOT_CFG2[6]

EIM_DA15 = BOOT_CFG2[7]

~igor

[norishinozaki]

Igor,

Thanks!

Best regards,

Nori Shinozaki