i.MX 8M Mini: SPI-bus native CS

[ristohedman]

Hi,

I would like to ask NXP experts about SPI (ECSPI). My company is switching to iMX8 and in order to desighn the HW we need to know these details.

I've been studying 

     IMX8MMRM.pdf 

     8.1 External Signals and Pin Multiplexing

    10.1 Enhanced Configurable SPI (ECSPI) 

And asked my EVA- manufacturer but have not got an answer:

      How are SPI chip selects SS1, SS2 and SS3 muxed to hardware pins, (or balls or pads - which way ever one calls them) ?? 

      I heard that NXP is recommending to use gpio for chip selects (in Linux??) - is that true and if is, why?

Best Regards,

Risto H.

[Yuri]

@ristohedman 
Hello,

   Customers can use Table 8-1 (Muxing Options) of the i.MX8Mm RM.
As for pin assignments - use section 5 (Package information and contact assignments)
of i.MX8Mm Datasheet.

https://www.nxp.com/docs/en/data-sheet/IMX8MMCEC.pdf

GPIO instead of "native" SS may be used for non supported modes, say for "long"
messages.

Regards,
Yuri.

[ristohedman]

Hi,

Hmmm, now I must have a great misunderstanding, if I try to search e.g. ECSPI1_SS1 in any 'mini'- related document, I can not find ??!!

br, ristoH

[Yuri]

@ristohedman 
Hello,

i.MX8Mm supports single eCSPI SS: ECSPI1_SS0 - there are no more (ECSPI1_SS1 ...).

https://community.nxp.com/t5/i-MX-Processors/How-can-I-use-ECSPI-SS1-2/m-p/848467

Regards,
Yuri.

[ristohedman · Accepted solution]

Hi Yuri,

Finally an answer - not a good one for me but answer anyway.

BR, ristoH