configuring i.MX93 ADC sampling rate

[yaen]

Hello NXP,

I'm working with the 12-bit ADC on an i.MX93. I'm looking for documentation on how to change the ADC sample rate. Specifically:

Is there a direct method to modify the ADC sample frequency?
If not, what parameters control the sample rate, and how can I adjust them?
Do I need to stop the ongoing conversion process before changing these parameters?
Is there a recommended sequence of steps to safely change the sample rate during operation?

I've consulted the available documentation https://www.nxp.com/docs/en/reference-manual/IMX_REFERENCE_MANUAL.pdf and in ch.4.1.6 it says that i should have a software intrerface sampling_frequency_available but i don't have it. I do have in_voltage_sampling_frequency but it doesn't receive any values that i tried. Any guidance or pointers to relevant documentation would be greatly appreciated.

[JorgeCas · Accepted solution]

Hello,

Please take a look on reference manual in section 72.3.4 ADC clock prescaler and sample time settings to check the sample time configuration:

"In order to support different sampling times for different type of channels the different conversion timing registers are used (CTR0, CTR1). CTR0 is associated to channels (0 to 31), CTR1 is associated to channels (32 to 63)."

The ADC calibration is the first step that should be run after every power-on reset to function correctly and configure SAR controller operating clock is part of this process to initialize it.

Best regards.

[Dev75]

Hello,

I have reviewed the section you mention as well as the Compulab imx93_adc.c driver, as well as I see that the freescale imx93.dtsi is included in the source for the device tree.   Within the freescale imx93.dtsi I see code for clocks ( see below ).  Could the 24000000 clock be for the adc?  When I read the in_voltage_sampling_frequency file it has 24000000 in it.  I have tried many values to try to change it but always get invalid argument ( even if I write the same 24000000 value).   

osc_32k: clock-osc-32k {

compatible = "fixed-clock";

#clock-cells = <0>;

clock-frequency = <32768>;

clock-output-names = "osc_32k";

};

osc_24m: clock-osc-24m {

compatible = "fixed-clock";

#clock-cells = <0>;

clock-frequency = <24000000>;

clock-output-names = "osc_24m";

};

clk_ext1: clock-ext1 {

compatible = "fixed-clock";

#clock-cells = <0>;

clock-frequency = <133000000>;

clock-output-names = "clk_ext1";

I know it is easy to say just review the device tree files and drivers; however, I have still yet to find the linkage between the file-sys names and the actual device tree and driver files.  Since NXP's imx93.dtsi is included I assume that you can help me determine how to find out what are valid arguments for this in_voltage_sampling_frequency.  I see this in the Compulab adc driver  ( it seems to be using the MCR register ).  Not sure how to link this function to the file-sys names either.

static void imx93_adc_config_ad_clk(struct imx93_adc *adc)

{

u32 mcr;

/* put adc in power down mode */

imx93_adc_power_down(adc);

/* config the AD_CLK equal to bus clock */

mcr = readl(adc->regs + IMX93_ADC_MCR);

mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);

writel(mcr, adc->regs + IMX93_ADC_MCR);

imx93_adc_power_up(adc);

}

Any guidance you can give on this is appreciate.  Please remember COmpulab posted this question first and similarly can't figure it out.  Seems much too difficult to figure out than it should be.

Thanks you.

[Dev75]

Hello again,

After further review I'm going to make a hypothesis about this situation in regards to changing the adc sample frequency.  Because of this note and the fact that the Compulab adc driver does not have a sysfs entry for controlling the power-down function, even though the driver function is in there, any value entered into the User sysfs in_voltage_sampling_frequency is rejected as invalid.

"72.3.4 ADC clock prescaler and sample time settings
The AD_CLK frequency can be scaled by programming MCR[ADCLKSE]. If MCR[ADCLKSE] is set, then the AD_CLK frequency
is the same as the bus clock. Otherwise, AD_CLK frequency is half of bus clock, MCR[ADCLKSE] bit can be written in power-down
only when MCR[PWDN] = 1.
In order to support different sampling times for different type of channels the different conversion timing registers are used
(CTR0, CTR1). CTR0 is associated to channels (0 to 31), CTR1 is associated to channels (32 to 63). See the register description
for details. "

In summary it appears that if I want to change the adc sampling frequency I have to update the adc.c driver to include the sysfs mapping and then compile and re-deploy to the target.  Then after that I should be able to power down the adc, and change the sampling frequency then power back up ( probably need to map this to sysfs as well ).

What do you think?  Have I "Sherlock-Holmes" this thing reasonably?

Thanks again for your support.

[Dev75]

Hello NXP support,

Because this NXP adc driver is limited in functionality, is there going to be enhancements made to this driver so things like changing the sample frequency can be done?  There are probably other nice features that could be added to this driver as well.  Please consider improvements.  Thank you!

// SPDX-License-Identifier: GPL-2.0+
/*
* NXP i.MX93 ADC driver
*
* Copyright 2023 NXP
*/

According to the spec, this ADC totally support 8 channels. i.MX93 contain this ADC with 4 channels connected to pins in the package. i.MX95 contain this ADC with 8 channels connected to pins in the package. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Fixes:  <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>