How to use the register CCM_ANALOG_PFD_528n of iMX6ULL

[mzl]

Dear NXP expert,

Here I have one question about the register CCM_ANALOG_PFD_528n of iMX6ULL.

In the reference manual, it mentions that this processor has 4 registers CCM_ANALOG_PFD_528n (n=0,1,2,3)

The PFD_528 control register provides control for PFD clock generation.

This register controls the 3-phase fractional clock dividers. The fractional clock

frequencies are a product of the values in these registers.

Address: 20C_8000h base + 100h offset + (4d × i), where i=0d to 3d

Then how to use these 4 registers? e.g. if I want to change PLL2.PFD0 clock frequency, then does it need to configure all the above 4 registers? Thanks.

[joanxie]

refer to the RM

• When writing 1 to XXX_SET bit fields, these registers allow setting the masked 1 bit
fields, while keeping unchanged all bit fields which remain on 0 logic state.
• When writing 1 to XXX_CLR bit fields, these registers allow clearing the masked 1
bit fields, while keeping unchanged all other bit fields which remained on 0 logic
state.
• When writing 1 to XXX_TOG bit fields, these registers allow inverting the logic
state of all masked 1 bit fields, while they keep unchanged the remaining bit fields
which were kept on 0 logic state.

you also can refer to the link as below

About use of SCT registers for CCM_ANALOG_PLL_ARM - NXP Community

these register all would affect clock frequency, if you just want to change the PLL2.PFD0 clock frequency, you can just set  CCM_ANALOG_PFD_528

[JohnYau]

Hello, dear NXP experts. I saw the official case of NXP clock_config_ocram.c to set the PFD0~3 of PLL2 in the official case of NXP, you need to first set the CLOCKGATE position 1, turn off the clock, then set FRAC, and finally set the CLOCKGATE position 0 as needed to turn on the clock. But this way, I found that imx6ull gets stuck. I removed the code to set the CLOCKGATE and only kept the code to set FRAC, which worked fine. What causes this?