Write leveling calibration returns wrong values on a DDR3 layout with T-topology

[peterlischer]

We have a product that uses an i.MX 6Q with Nanya DDR3 RAM in a 64bit configuration (total 1GByte RAM, 4 x16 chips with 2Gb capacity). The DDR3 RAM is routed with a T-topology and the trace length are the following:

• CLK0/CLK1: 51.00mm
• Address/Command lines: All between 50.41mm and 50.64mm (measured from controller pad to any of the RAM chips)
• DQS0: 21.96mm
• DQS1: 22.72mm
• DQS2: 27.92mm
• DQS3: 22.5mm
• DQS4: 28.48mm
• DQS5: 22.26mm
• DQS6: 23.2mm
• DQS7: 21.48mm

The first bit of each byte group are connected without swapping, the rest of the bits are swapped according to the layout needs. The bit (DQ) signals and the DQM signal of each byte group are matched to its according DQS signal.

I have created a configuration file with the "Mx6DQSDL DDR3 Script Aid V0.09.xlsx" and I am running the "DDR_Stress_Tester_V1.0.3". The write leveling calibration returns me the following results: 

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x017C000A

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00120006

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x017F0014

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x017F0008

The delay values for 3 of the 8 bytes are extremely high, they are almost one clock cycle. When I run the DQS gating, read/write delay calibration afterwards, it fails ("ERROR FOUND, we can't get suitable value !!!!") and also the stress test is failing at any selected speed.

According to my calculations by taking in account the signal lengths, the correct write level calibration should be the following:

MMDC_MPWLDECTRL0 ch0:  0x001A001A

MMDC_MPWLDECTRL1 ch0:  0x001A0015

MMDC_MPWLDECTRL0 ch1:  0x001A0014

MMDC_MPWLDECTRL1 ch1:  0x001B0019

When I enter these values into the configuration file and skip the write level calibration, the DQS gating delay calibration is working fine and the stress test even works with the maximum frequency of 672MHz without giving any error.

I do not think there is anything wrong with the layout, since it even runs with the highest frequency without any problems. The question is why the write leveling calibration is outputting these wrong numbers. As far as I understand, the write leveling calibration is mainly needed when using a fly-by topology. Is it recommended in my case just to skip the calibration and use either the calculated values or the standard values of 0x001F001F (which also work without any problems)?

Thank you all in advance for any help.

[yizheng]

I have the same problem. HW write-leveling gives bad value.

Please refere to the doc:  i.MX 6 Series DDR Calibration(AN4467)

    "Although not required, T-Topologies may also benefit from performing

    Write Leveling as there are package delays on both the processor and DDR

    devices that can be de-skewed by performing Write Leveling. Therefore,

    Freescale recommends determining Write Leveling calibration parameters

    for all boards, regardless of topology used."

I would think that the HW write-leveling is not correctly implemented by SoC.

Any one agree with me?

[Yuri · Accepted solution]

  Strictly speaking,  Write Leveling should be used with fly-by topology, and in this sense it
is quite reasonable to skip Write Leveling when T-topology is applied. In the same time,
even for T-topology, it should be possible to get much closer alignment of SDLCK edge
with DQS edge if the Write Leveling Calibration procedure is used to find proper calibration

values.

Have a great day,
Yuri

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