Why MMPF0100 VREFDDR startup few late?

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Why MMPF0100 VREFDDR startup few late?

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torus1000
Contributor V

Dear Analog experts,

I'm not familiar with OP Amp.
When I measured MMPF0100/F0 PMIC output timing, most of SWx turned on just in time(Sq# x 2ms).

Why only VREF DDR output so delayed to start turn-on?

It seems to kept on low around 400us.

Can anybody help me?

Thanks

vref_ddrQ.png

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reyes
NXP TechSupport
NXP TechSupport

Hi,

This delay that you are seen is probably caused by a big capacitance in the layout VREFDDR line, I believe that this delay can probably be adjusted by modifying the output capacitor value on VREFDDR pin. Try using a lower value capacitor.


Have a great day,
Jose Reyes

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reyes
NXP TechSupport
NXP TechSupport

Hi,

This delay that you are seen is probably caused by a big capacitance in the layout VREFDDR line, I believe that this delay can probably be adjusted by modifying the output capacitor value on VREFDDR pin. Try using a lower value capacitor.


Have a great day,
Jose Reyes

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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torus1000
Contributor V

BTW

I reviewed VINREFDDR then found SW3AB supplied 1.5V to VINREFDDR.
Suppose if VINREFDDR>0.8V then mos FET goes ON, it takes 512us where slewrate set 25mV/16us.

BR

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