WatchDog Issue

[annie_varshitha]

Im using MCIMX6Y2CVM08AB processor where GPIO1_IO08 is configured as WDOG_B.

This signal is given to an AND gate which in turn controls the enable of the regulator.

During initial power up (just after production), the AND GATE output is held low because of the initial state of the watchdog.

Is there any solution for this?

Whether this signal will be high by default (without programming)?

Attached is the AND GATE section.

[igorpadykov]

Hi annie_varshitha

in general pin state is described in Table 91. 14 x 14 mm Functional Contact Assignments

column "Out of Reset Condition" and can not be changed.

i.MX 6ULL Applications Processors for Consumer Products

Best regards
igor

[annie_varshitha]

Could you elaborate on the below statements: when and how is it to be used ?

>WDOG1_ANY : Global WDOG signal

>WDOG1_B : This signal will power down the chip.

>WDOG1_RST_B_DEB : This signal is a reset source for the chip.

I am using GPIO1_IO08 as WDOG_B with ALT1 mux option.

But  the signal is low (from the processor) even after configuring it.

What would be the reason?

[igorpadykov]

please refer to description in Chapter 59  Watchdog Timer (WDOG)

i.MX 6ULL Applications Processor Reference Manual

WDOG1_ANY is the global watchdog signal.

It goes low if “any” of the WDOGx_B signals assert.

Best regards
igor