From the Design Checklist of the Hardware Development Guide for i.MX 6 :
If feeding an external clock into the device, XTALI can be driven DC-coupled with XTALO floated.
The XTALI signal level must swing from ~80% of NVCC_PLL_OUT to ~0.2V.
So,
1.
> Can the the XTAL pins be driven by a 1.8V clock source?
No.
2.
> Can the CLK pins be used instead of the XTAL pins?
No. 24 MHz is default ref. clk for the PLLs after reset.
Therefore 24 MHz is needed at least for startup.