UART1 not receiving data in DTE mode

[koejul]

Hey there.
We are trying to configure UART1 in DTE mode as our product will mainly interface with modems and other DCE hardware.
When configuring UART1 to DCE mode in the device tree, data gets sent out of the correct pin and gets correctly received after connecting RX and TX straight through.
But when UART1 is configured to DTE mode, the data gets sent out of the RX pin. So far so good. DTE mode seems to work.
But when trying to read the content of UART1 in the console by the help of "cat /dev/ttymxc0", no data is displayed. When executing the same command in DCE mode, the sent data is displayed.
Our device tree is pasted below. The commented parts are for UART1 in DCE mode. No hardware handshake is used ATM. Also attached is the latest bootlog of the system. I have also tried to configure UART3 into DTE mode which works without a problem. The sent out data is received and shown in the console.

Am I missing something with the configuration of UART1?

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 * Copyright 2019-2021 Variscite Ltd.
 */

#include "imx8mm-var-som-embcustom.dtsi"

/ {
	model = "Variscite VAR-SOM-MX8M-MINI on a.Box FSD rev2021";

	chosen {
		bootargs = "console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200";

		bootargs-append = "console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200 androidboot.console=ttymxc3 androidboot.primary_display=imx-drm androidboot.board=varsommx8mmini androidboot.bt_uart=/dev/ttymxc1 androidboot.bt_sdio=/sys/bus/mmc/devices/mmc0:0001/mmc0:0001:1/device androidboot.bt_firmware=BCM43430A1.hcd androidboot.bt_sdio_id=0xa9a6 androidboot.wificountrycode=CN";
		stdout-path = &uart4;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 1000000 0>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <80>;
		status = "okay";
	};

	gpio-keys {
		compatible = "gpio-keys";
		status = "okay";

		wakeup {
			label = "Wakeup";
			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
			linux,code = <143>;
			wakeup-source;
		};
	};
};

&i2c3 {
	/* Capacitive touch controller */
/*	ft5x06_ts: ft5x06_ts@38 {
		compatible = "edt,edt-ft5206";
		reg = <0x38>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_captouch>;
		interrupt-parent = <&gpio5>;
		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
		touchscreen-size-x = <800>;
		touchscreen-size-y = <480>;
		touchscreen-inverted-x;
		touchscreen-inverted-y;
		wakeup-source;
		status = "okay";
	};
*/
	/* DS1337 RTC module */
	rtc@68 {
		compatible = "dallas,ds1337";
		reg = <0x68>;
		status = "okay";
	};
};
/*
&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	port {
		mipi1_sensor_ep: endpoint@1 {
			remote-endpoint = <&ov5640_mipi1_ep>;
			data-lanes = <2>;
			csis-hs-settle = <13>;
			csis-clk-settle = <2>;
			csis-wclk;
		};

		csi1_mipi_ep: endpoint@2 {
			remote-endpoint = <&csi1_ep>;
		};
	};
};

&csi1_bridge {
	fsl,mipi-mode;
	status = "okay";

	port {
		csi1_ep: endpoint {
			remote-endpoint = <&csi1_mipi_ep>;
		};
	};
};
*/
&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&pwm2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
};

/* Full Serial UART, LSA Modems e.g. */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	fsl,dte-mode;
/*	fsl,uart-has-rtscts;	*/
	status = "okay";
};

/* IBIS UART */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

/* Console via FTDI Converter */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	/delete-property/ dmas;
	/delete-property/ dma-names;
	status = "okay";
};

&usbotg1 {
	dr_mode = "peripheral";
	picophy,pre-emp-curr-control = <3>;
	picophy,dc-vol-level-adjust = <7>;
	srp-disable;
	hnp-disable;
	adp-disable;
/*	extcon = <0>, <&extcon_usb1>;	*/
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
/*	vbus-supply = <&reg_usb_otg2_vbus>;	*/
	picophy,pre-emp-curr-control = <3>;
	picophy,dc-vol-level-adjust = <7>;
	disable-over-current;
	status = "okay";
};

/* SD */
/*
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};
*/

&gpio1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio1>;
	status = "okay";
};

&gpio2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio2>;
	status = "okay";
};

&gpio4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio4>;
	status = "okay";
};

&gpio5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio5>;
	status = "okay";
};
/*
&snvs_pwrkey {
	status = "okay";
};

&snvs_rtc {
	status = "disabled";
};
*/
&iomuxc {

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT		0x06
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x06
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX		0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX		0x140
			MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B		0x140
			MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B		0x140
		>;
	};

/*	pinctrl_uart1: uart1grp {	*/
/*		fsl,pins = <		*/
/*			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x140	*/
/*			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x140	*/
/*			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B		0x140	*/
/*			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B		0x140	*/
/*		>;	*/
/*	};		*/

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x140
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x140
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x140
		>;
	};

	pinctrl_gpio1: gpio1grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x16	/*DISP_BL_W_SHDN*/
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x16	/*DISP_BL_G_SHDN*/
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x16	/*SOM_Alive*/
			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x16	/*var_DC_EN*/
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x16	/*DO1_EN*/
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x16	/*LED 0*/
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x16	/*I_IGN*/
			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x16	/*24V_1A_2_EN*/	
			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x16	/*Wake pin from watchdog*/		
		>;
	};

	pinctrl_gpio2: gpio2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13			0x16	/*I_Signal_2*/
			MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15		0x16	/*I_Signal_4*/
			MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16		0x16	/*I_Signal_3*/
 			MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17		0x16	/*I_Signal_1*/
			MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18		0x16	/*I_Signal_C4*/
			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x16	/*SHDN_2V5*/
		>;
	};

	pinctrl_gpio4: gpio4grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x16	/*OPT_OUT_1_EN*/
			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11		0x16	/*varDC_SHDN*/
			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21		0x16	/*DISP_DATA_COM*/
			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x16	/*SHDN_1V2*/	
			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x16	/*ETH_SW_RST*/
			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26		0x16	/*24V_3A_EN*/
			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x16	/*KSZ8091_RST*/
			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x16	/*BB_SHDN*/
		>;
	};

	pinctrl_gpio5: gpio5grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1			0x16	/*DO2_EN*/
			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x16	/*5V_EN*/
			MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x16	/*LED 1*/
			MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11		0x16	/*24V_1A_1_EN*/
			MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12		0x16	/*OPT_IN*/
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x16	/*OPT_OUT_2_EN*/
			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x16	/*USB_HUB_RST*/
			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x16	/*LAN9513_RST*/
			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x16	/*DISP_BL_R_SHDN*/
			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x16	/*CAN_STBY*/
		>;
	};
};

[Sanket_Parekh]

Hi @koejul 

I hope you are doing well

Please note that in dte-mode RTS/CTS and TX/RX pins will be swapped.

Kindly share the schematic for more debugging on how you are connecting the processor and end device through UART.

Thanks & Regards

Sanket Parekh

[koejul]

Hi @Sanket_Parekh 

I am doing fine, thanks.

We are aware of RTS/CTS and TX/RX being swapped.

Unfortunately, we are not able to share the used schematics as we are not aware of how far they are confidential. But in the end following balls are used:

UART1 is used in DTE mode.
Data is transmitted and measured on ball SOC.E14 and looped to ball SOC.F13. But in software, no data is read on the RX pin.

When UART1 is set to DCE mode, data is transmitted and measured on ball SOC.F13 and looped to ball SOC.E14. Data is read in software and output via "cat /dev/ttymxc0".

We are using a Variscite VAR-SOM-MX8M-Mini SOM on the Symphony evaluation board of Variscite.

Thanks & regards

Julian

[Sanket_Parekh]

Hi @koejul 

I hope you are doing well

Please add(uncomment) the "uart-has-rtscts" property in the device tree. It is necessary to enable this property for RS485, and please check again if it is working or not.

Thanks & Regards

Sanket Parekh

[koejul · Accepted solution]

Hi @Sanket_Parekh 

The solution has been found by the help of variscite support.

changing line 604 in /arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h# to

define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX    0x238 0x4A0 0x4F4 0x0 0x1

resolved the issue.

Unfortunately, it seems as we are the first using UART1 in DTE mode and thus, this bug stayed unrecognised until now.

This case can be closed.

Thanks & Regards

Julian