Setting up external oscillator to SSI

[robyf]

Hi All,

I'm setting up a custom board providing an external oscillator for the SSI to control an audio device, the oscillator provide 2.048KHz clock to SSI but the SSI as to generate the frame sync for the TDM. I've setup both SSI and AUDMUX accordingly but I guess there is also the PLL4 clock side to set, see in http://cache.freescale.com/files/32bit/doc/app_note/AN4952.pdf.

I'm not really sure how to do it in the kernel file clk-imx6sx.c, does anyone can help here and suggest the related changes?

Thanks in advance,

Roberto Fichera.

[igorpadykov]

Hi Roberto

PLL4 provides SSI_CLK_ROOT and this initialization is already

present in clk-imx6sx.c. Regarding external oscillator it may be only necessary

to check requirement from  i.MX6SX  RM  sect.62.8.4 SSI Clocking :

Care should be taken to ensure that the bit clock frequency (either internally generated by

dividing the SSI's sys clock or sourced from external device through Tx/Rx clock ports)

is never greater than 1/5 of the ipg_clk (from CCM) frequency.

Best regards

igor

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[robyf]

Hi Igor,

The same board running with the internal clocking works fine. Now I'm testing a variant having an external oscillator. ipg_clk is currently running at 66MHz, at least this is what the clk_get_rate() is reporting. Wandering to know if the SD3_DATA1 configured in ALT3, need the SION bit set in case of external oscillator, maybe yes.

[igorpadykov]

no, sion bit is not necessary for providing ssi external clock.

Sufficient to set correct pad iomux settings.

~igor

[robyf]

Hi Igor,

Do you think the settings below are correct?

		pinctrl_audmux_1: audmuxgrp-3 {
			fsl,pins = <

                MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC    0x130b0    /* PCLK */

                MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS   0x130b0    /* FSYNC */

                MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD    0x130b0    /* DTX */

                MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD    0x120b0    /* DRX */

			>;
	};