SSI TDM mode master clock configuration issue?

[dp_yanam]

Hi all,

I was new to SSI TDM mode. we are trying to interface 24-bit frame sync ADC to SSI lines in imx6 board. I had written driver for initialising the SSI in TDM mode. I could able to achieve interface is working. ADC is responding with data with two channels. 

Right now i was facing any sampling rate issue. I could able to generate master clock from SSI lines upto 12MHz and sampling rate(frame sync clock) 20Kbps. we want to configure the ssi master clock 24Mhz & sampling rate 48Khz.

anyone please tell me how to configure the master clock & sampling rate as per my need.

we are using yocto 4.9.88. please suggest me any solution to configure the master clock with required frequency.

I attached driver file below for all your reference.

Thanks in advance.

Regards,
K. durgaprasad.

[dp_yanam]

Hi Igor,

thanks for your reply. After long time, I was reworking on the ssi clock. we could able to achieve the ssi tdm mode. we facing problem with noise in the signals with ADC chip. We want to configure for 24Mhz bit clock from SSI port.

Can you please let me know if any configurations are required for pll4 or ssi settings to get 24Mhz bit clock & frame sync clock 48kHz.

[igorpadykov]

Hi Durgaprasad

for ssi one can look at simple sdk baremetal examples

(zip can be found on link https://community.nxp.com/thread/432859 )

and use them as reference.

Best regards
igor
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