SPI without MISO

[mustafademirci]

Instead of building an SPI port with MOSI and MISO lanes, is it possible to have two symmetric seperate SPI interface with only MOSI lanes between i.MX6 and an FPGA?

[igorpadykov · Accepted solution]

HI Mustafa

seems one can use configuration with

one interface as master, other slave.  One can look at

IMX6DQRM  sect.21.1.2 Modes and Operations

Best regards

igor

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