Request of timing model (.v) for LPPDR4 simulation using Hyperlynx.

[puiyee_poon]

Hi, I am simulating the LPDDR4-interface and Hyperlynx request a timing model file (*.v). Can you please provide me with this file? The device I am using is MIMX8ML4CVNKZAB and the ibis-model is imx8mp_15x15_v2.ibs. Thank you in advance! Br // PuiYee

[Rita_Wang]

You can use the MSCALE DDR Tool provided by NXP:

i.MX 8M Family DDR Tool Release - NXP Community

Any questions contact me freely

Wish you have a nice day

Best Regards

Rita

[puiyee_poon]

Hi,

The tool that you recommend is of use when we have the board in reality. But I'm in a phase that we have just routed the layout and need to do simulations between the LPDDR4 and i.MX8MPlus-processor to make sure that the signal quality is good before producing the PCBA.
So please provide me with the Verilog Design File-file (*.v) for MIMX8ML4CVNKZAB as requested so I can implement the file in the Hyperlynx-tool to do my simulations. Thank you in advance!

Br // PuiYee

[Rita_Wang · Accepted solution]

Hi @puiyee_poon ，

I give the update to you in the case, please check it.

Wish you have a nice day

Best Regards

Rita

[Rita_Wang]

Hi @puiyee_poon ,

I am confirming it for you, please wait.

Wish you have a nice day

Best Regards

Rita