Reading clock rate value and the actual measured value are differenc for the LVDS clock signal on Yocto

[charleshuang]

I refer to the following URL.

Reference URL: https://community.freescale.com/thread/306801

I set a frequency of 29.5 MHz for the PLL5 LVDS clock signal on Yocto 3.10.17.1.0.2, the value is close to 29.5 MHz by oscilloscope.

But the clock rate value of pll5 video is close 206.5 MHz on console log.

Console log:

# cat /sys/kernel/debug/clk/osc/pll5_video/pll5_post_div/pll5_video_div/clk_rate

206499990

#  cat /sys/kernel/debug/clk/osc/pll5_video/pll5_post_div/pll5_video_div/ldb_di0_sel/clk_rate

206499990

Can you tell me why reading clock rate value and the actual measured value are difference?

Thank you.

Best Regards,

Alex Cheng

[alejandrolozan1]

Hi,

Which modifications did you perform?

Can you provide the details?

Best Regards,

Alejandro

[charleshuang]

Hi Alejandro,

I modify two files.

1) File: arc/arm/mach-imx/clk-imx6q.c. In imx6q_clocks_init():

/* ipu clock initialization */

-  init_ldb_clks(pll2_pfd0_352m);

+ init_ldb_clks(pll5_video_div);

2) File: drivers/video/mxc/ldb.c. Add a new mode in ldb_modedb[ ]:

static struct fb_videomode ldb_modedb[] = {

#ifdef CONFIG_ARCH_ADVANTECH

  {

  "LDB-XGA", 60, 1024, 768, 15385,

  220, 40,

  21, 7,

  60, 10,

  0,

  FB_VMODE_NONINTERLACED,

  FB_MODE_IS_DETAILED,},

+         {

+         "LDB-VGA", 60, 640, 480, 25175,

+          220, 40,

+           21,  7,

+           60, 10,

+            0,

+          FB_VMODE_NONINTERLACED,

+          FB_MODE_IS_DETAILED,

+         },

{

  "LDB-WXGA", 60, 1360, 768, 14148,

  158, 1,

Can you tell me why reading clock rate value and the actual measured value are difference?

Thank you.

Best Regards,

Alex Cheng

[jim_lin]

the correct path to read LVDS clock is:

/sys/kernel/debug/clk/osc/pll5_video/pll5_post_div/pll5_video_div/ldb_di0_sel/ldb_di0_div_7# cat clk_rate

FYI~