Reading Memory ID on i.MX 93 SoC

[yentin]

Dear NXP Technical Support,

I would like to know if there is a way to share the DDR size found in SPL with U-Boot.

In the i.MX 8 series, we used the OCRAM Free Memory Space for this, but it seems to be locked in the i.MX 93. Can I use the 8K init area safely, for example at address 0x20490000? What is this area used for?

Thank you for your time and consideration.

Sincerely,

Yaakov Entin.

[yentin]

Hi Harvey,

Thanks for your reply. I'll try to explain my question in more detail.

The DDR size can vary depending on the customer's order. I want to use the DDR size that SPL detected and initialized rather than hard-coding it in U-Boot. This way, I can avoid having to create a separate U-Boot image for each possible DDR size.

To pass the DDR size from SPL to U-Boot, I need to use a medium that can be accessed by both. The only medium that meets this requirement is the OCRAM 8K init area.

In the i.MX 8 series, we used the OCRAM Free Memory Space and TCM areas to share the DDR size. However, these areas are locked in the i.MX 93.

I'm wondering if it's safe to use the 8K init area in the i.MX 93 to share the DDR size. If so, can you tell me what this area is used for? The DDR size is stored in a 16-bit value.

I appreciate your help with this.

Best regards,
Yaakov Entin

[dtony]

Maybe you can try  HANDOFF, which can passes information from spl to uboot. 

No any depends on a certain chip such as tcm,  ocram. 

That is a common way, like uboot bootargs passing kernel parameters to linux kernel. 

https://community.nxp.com/t5/i-MX-Processors/SPL-to-u-boot/m-p/1654311#M206234

[Harvey021]

Hi @yentin 

This area is used internally by the ROM and can be used at will when entering the user stage. 

It is safe to use.

Best regards

Harvey

[yentin]

Thanks!

BTW, why are OCRAM Free Memory Space and TCM areas locked in the i.MX 93?

[Harvey021]

Hi @yentin 

I don't quite understand what you mean.

The default SPL is running in OCRAM, U-BOOT is running in DDR. 

Can you explain more for your question?

Best regards

Harvey

[dtony · Accepted solution]

Because there is TRDC of i.MX93. 

Has TRDC configuration to assign different domain.

You can check the reference manual and atf source code to know that. 

Still, I think it is a very bad way to use hardware/chip pass the information from spl to u-boot. 

u-boot has mechanism HANDOFF to do so. Actually, if you read the handoff source code. 

The defaut case is to pass the memory information from spl to u-boot. 

// SPDX-License-Identifier: GPL-2.0+
/*
 * Passing basic information from SPL to U-Boot proper
 *
 * Copyright 2018 Google, Inc
 */

#include <common.h>
#include <handoff.h>
#include <asm/global_data.h>

DECLARE_GLOBAL_DATA_PTR;

void handoff_save_dram(struct spl_handoff *ho)
{
	struct bd_info *bd = gd->bd;
	int i;

	ho->ram_size = gd->ram_size;

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		ho->ram_bank[i].start = bd->bi_dram[i].start;
		ho->ram_bank[i].size = bd->bi_dram[i].size;
	}
}

void handoff_load_dram_size(struct spl_handoff *ho)
{
	gd->ram_size = ho->ram_size;
}

void handoff_load_dram_banks(struct spl_handoff *ho)
{
	struct bd_info *bd = gd->bd;
	int i;

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		bd->bi_dram[i].start = ho->ram_bank[i].start;
		bd->bi_dram[i].size = ho->ram_bank[i].size;
	}
}

[dtony]

Harvey.

Could not remember? just 2 months ago. 

https://community.nxp.com/t5/i-MX-Processors/SPL-to-u-boot/m-p/1654311#M206234