RMII interface on i.mx6 Solo

[alexberenshtein]

We use i.mx6 - Solo. We changed interface from RGMII to RMII. We use Marvell 88E6020 ,  have 2 steps.

1. In U-Boot:

MX6_PAD_ENET_MDIO__ENET_MDIO|MUX_PAD_CTRL(ENET_PAD_CTRL) , MX6_PAD_ENET_MDC__ENET_MDC|MUX_PAD_CTRL(ENET_PAD_CTRL) , MX6_PAD_ENET_CRS_DV__ENET_RX_EN|MUX_PAD_CTRL(ENET_PAD_CTRL) , MX6_PAD_ENET_RX_ER__ENET_RX_ER|MUX_PAD_CTRL(ENET_PAD_CTRL) , MX6_PAD_ENET_TX_EN__ENET_TX_EN|MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RXD0__ENET_RX_DATA0|MUX_PAD_CTRL(ENET_PAD_CTRL) , MX6_PAD_ENET_RXD1__ENET_RX_DATA1|MUX_PAD_CTRL(ENET_PAD_CTRL) , MX6_PAD_ENET_TXD0__ENET_TX_DATA0|MUX_PAD_CTRL(ENET_PAD_CTRL) , MX6_PAD_ENET_TXD1__ENET_TX_DATA1|MUX_PAD_CTRL(ENET_PAD_CTRL) , MX6_PAD_GPIO_16__ENET_REF_CLK|MUX_PAD_CTRL(0x4001b0a8),

Working OK !!!!!!;

In kernel 4.1.15:
pinctrl_enet:

                enetgrp { fsl,pins =

< MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0

  MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0

 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN

 0x1b0b0 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER

 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN

 0x1b0b0 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0

 0x1b0b0 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1

  0x1b0b0 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0

 0x1b0b0 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0

  MX6QDL_PAD_GPIO_16__ENET_REF_CLK  0x4001b0a8 >;

};

pinctrl_enet_irq: enetirqgrp

 { fsl,pins = < MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x000b1 >; }

Clock we get from MARVELL (50Mgz).

#define  MX6QDL_PAD_GPIO_16__ENET_REF_CLK   0x214 0x5e4 0x80c 0x12 0x0

Clear Bit 21 -> IOMUXC_GPR1[21] , Clock from Marvell !!!

 regmap_update_bits(gpr, IOMUXC_GPR1,IMX6Q_GPR1_ENET_CLK_SEL_MASK,0);

But , we get a message:  fec 2188000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=2188000.ethernet:18, irq=-1) IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready done.

What a problem ?

[alexberenshtein]

Hi Igor.

I see on terminal:

[    8.781755] fec 2188000.ethernet eth0: no PHY, assuming direct connection to switch
[    8.791175] libphy: PHY fixed-0:00 not found
[    8.797571] fec 2188000.ethernet eth0: could not attach to PHY

Best regards

[igorpadykov]

Hi Alex

one can debug it, starting from probe function, please use attached

Linux Manual and AN4553 Using Open Source Debugging Tools forLinux on i.MX Processors

http://cache.nxp.com/files/32bit/doc/app_note/AN4553.pdf 

linux-2.6.35.3-imx28/mv88e6020.c at master · embeddedarm/linux-2.6.35.3-imx28 · GitHub 

nxp has service for helping porting drivers: NXP Professional Services:

http://www.nxp.com/support/nxp-professional-services:PROFESSIONAL-SERVICE

Best regards
igor

[alexberenshtein]

Hi Igor.

Yes.

phy gpio reset is is  working good    0 / 1.

We get clock from Marvel.

bit GPR[21]=0 ---> Get clock from external .

IOMUXC_SW_MUX_CTL_PAD_GPIO16 ---> address 20E0214h

bit SION =1 -> ENABLED — Force input path of pad GPIO_16

MUX_MODE -> 010 (ALT2) -> select signal ENET_REF_CLK

About patch - I use kernel 4.1.15 - with all patches.

Best regards.

[alexberenshtein]

Hi Igor.

Yes.

We have :

 dts file in RMII  :

&fec { ..     phy-mode = "rmii";

MAC is OK.

[igorpadykov]

Hi Alex

is there phy gpio reset, is it working properly
&fec {.. 
MX6_enet_RMII.zip on 
 https://community.nxp.com/thread/304346?commentID=331971#comment-331971      

Best regards
igor

[igorpadykov]

Hi Alex

has dts file rmii entry as in examples:

&fec { ..     phy-mode = "rmii";

linux-2.6-imx.git - Freescale i.MX Linux Tree 

https://community.nxp.com/message/841332?commentID=841332#comment-841332 

also one can check mac address as in attached Linux Manual

sect.43.3.2 Getting a MAC Address

Best regards
igor
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