Questions about DDR3 configuration details, iMX6DL

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Questions about DDR3 configuration details, iMX6DL

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jaripeltonen
Contributor IV

Hi,

I am working on SW for a product that is based on iMX6 Dual Lite processor.
SDRAM clock frequency is 400MHz (clock cycle 2.5ns).
We are planning to change SDRAM to a bigger one and one candidate for the new SDRAM is a DDR3-1866 (-107) component.

Timing values for this SDRAM are; tRC for it is 47.91ns, tRAS is 34ns and tFAW is 35ns (2KB page size).

MMDC configuration values would then be tRC=20CK, tRAS=14CK and tFAW=14CK, respectively.

Is this correct? Would these values work ok on our HW?

 

Best regards,
Jari

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jaripeltonen
Contributor IV

Hi Yuri,

Thanks for your comments and support!

I have no further questions. I will close this thread.

Thanks & best regards,

Jari

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jaripeltonen
Contributor IV

Hi Yuri,

Thanks for your comments and support!

I have no further questions. I will close this thread.

Thanks & best regards,

Jari

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jaripeltonen
Contributor IV

Hi Yuri,

Thanks again for your answer!

I see your point. And, then again, it is interesting to notice that in the actual source code for Sabre MX6DL
(e.g. https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx6sabresd/mx6dlsabresd.cf...
the two bytes MDCFG0 and MDCFG1 are set to these values;

DATA 4 0x021b000c 0x3F435313
DATA 4 0x021b0010 0xB66E8B63

The first register equals to timing values
tRFC = 160ns
tXS = 170 ns
tXP = 7.5 ns
tXPDLL = 10CK
tFAW = 45 ns = 18 CK
tCL = 13.5 ns

And the second register equals to timing values
tRCD = 13.5 ns
tRP = 13.5 ns
tRC = 49.5 ns = 20 CK
tRAS = 36 ns
tRPA = 1 CK
tWR = 15 ns
tMRD = 12 CK
tCWL = 5 CK

When looking at timing parameters tFAW and tRC, they relate to DDR3-1333 (666 MHz), not to 400 MHz (or MX6DL max freq 528 MHz).
I'm just wondering how they ended up using these values for Sabre MX6DL...?

Best regards,
Jari

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   I think, when using memory DDR3-1333 timing parameters under 400 MHz, we are not

fully on safe side. But it may work.    

Regards,

Yuri.

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jaripeltonen
Contributor IV

Hi Yuri,

Unfortunately it seems I am not getting answers to my original questions...
I do understand your point on safe values. But what is wrong in using the values that are calculated from the SDRAM specific values?

For example, if tRC of the chosen SDRAM is 47.91ns, this parameter is SDRAM specific, not iMX6DL or MMDC specific, right?
So, in order to meet the tRC requirement of this specific SDRAM, we need to tell MMDC to set tRC to 20CK.
Is my conclusion correct? Using this value, would the SDRAM work without issues and safely on iMX6DL HW?

Best regards,

Jari

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   Your considerations makes a sense,  the  only comment here is that taking

tRC as 47.91 ns  relates DDR3L-1866 specs, that is, such tRC is tested and guaranteed

for  memory frequency 933 MHz. In Your system the frequency is 400 MHz.

Regards,

Yuri.

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jaripeltonen
Contributor IV

Hi Yuri,

Thanks for your answer.
I agree and understand that timings should be set to safe values.
But this thread, as well as the "SDRAM configuration of iMX6DL / Sabre" thread,
contained specific questions regarding specific timing values and I would appreciate if you could
give me more concrete answers. I just want to learn the logic behind the derived values.

So, assuming that the SDRAM is of type DDR3-1866 (-107) and SDRAM clock runs at 400MHZ on iMX6DL.
Timing values for this SDRAM are; tRC=47.91ns, tRAS=34ns and tFAW=35ns (2KB page size).
MMDC configuration values would then be tRC=20CK, tRAS=14CK and tFAW=14CK, respectively.

Using these values, would the SDRAM work without issues and safely on iMX6DL HW?
If my calculations above are wrong, please let me know what I am calculating wrong
and why should I not use the DDR3-1866 specific values when calculating the timing values?

Best regards,
Jari

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Yuri
NXP TechSupport
NXP TechSupport

Hi, Jari!

   As an example, using memory Datasheet, linked below:

tRC  50.625 - 52.5 ns (DDR3L-1066)

tRC 49.5 – 51 ns (DDR3L-1333)

tRC 48.75 ns (DDR3L-1600)

tRC 47.91 ns (DDR3L-1866)

 

  From my point of view tRC specs for DDR3L-1066 is more preferable, since it is close 

to our working point DDR3-800. Also, some reasonable parameter values for  DDR3L-800

may be found in Table 29 (DDR3L Timing Parameters Used for IDD Measurements – Clock Units)

https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/2gb_1_35v_ddr3l...

Regards,

Yuri.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

 

  I think the recommendations in the following Community thread may be also

applied for this case.

SDRAM configuration of iMX6DL / Sabre 

  When considering the timing values, DDR3-800 should be taken, assuming 400 MHz as

working frequency. General idea is to use more safe (relax) values.

 

Have a great day,

Yuri.

 

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