Question regarding input_reg offset in imx8mn-pinfunc.h

[heiko]

Hi

I have trouble understanding the imx8mn-pinfunc.h (I think the question is not specific to the imx8mn).

The header starts off with this documentation:

/*
 * The pin function ID is a tuple of
 * <mux_reg conf_reg input_reg mux_mode input_val>
 */

As an example lets look at this line:

#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2           0x1E4 0x44C 0x000 0x5 0x0

My understanding is

offset mux_reg = 0x1E4

offset conf_reg = 0x44C

offset input_reg = 0x000

value written to mux_reg = 0x5

value written to input_reg = 0x0

Here is my question, why is the offset for the input_reg given with 0x000 ?

I can see in the ref-manual that the corresponding register has the offset 0x5C0.

Why is it given with 0 in the header?

It came to my eye that a lot of other macros give 0x000 as offset for the input_reg. It seems like all macros where the input_val = 0x0 have the offset 0x000 for the input_reg.

Why is it like that ?

Is a OR operation used to apply the value to the register and in the case of value 0x0 that wouldn't make any difference so the offset for the register isn't important and wasn't given correctly ?

Can someone help me understand ?

Thanks in advance

[Dhruvit]

Hi @heiko,

I hope you are doing well.

Daisy chain input select is only available in some module pins.

Please refer to 8.2.2.4 Daisy chain - multi pads driving same module input pin in i.MX 8M Nano Applications Processor Reference Manual for more information.

In above case, 

#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2           0x1E4 0x44C 0x000 0x5 0x0

Here, SAI3_MCLK -> selected pad for GPIO5_IO2 signal pin.
          GPIO5_IO2 -> GPIO5 module pin.

Here, GPIO5_IO2 pin does not have daisy chain inpul select functionality.

And register offset 0x5C0 is for SAI3_MCLK module pin and not for GPIO5_IO2 pin.

Daisy chain inpul select is only required for few module pins (offset 4BCh - 05F0 ).

offset 0x000 is for pins that do not have daisy chain input select functionally (e.g. GPIO5_IO2)

I hope it helps!

Thanks & Regards,
Dhruvit Vasavada