Question, i.MX6S SPDIF_SR_CLK

[Aemj]

Hi All,

I would like to ask about SPDIF_SR_CLK on i.MX6Solo.

My customer wants to use SPDIF Rx Clock for external Codec device.

In Figure 59-2 ‘SPDIF transceiver Clock Diagram’ in i.MX6SDL reference manual, we can see SPDIF Rx Clock which is produced from SPDIF_IN flows out from DPLL.

The customer wants to use this SPDIF Rx clock for external audio codec chip.

(1)

Is it possible to output this SPDIF Rx clock from SPDIF_SR_CLK pin?

If it is not possible, do you have any ideas to output the clock from i.MX6(from other pin via other route)?

(2)

If it is possible to output the clock from i.MX, please let me know the accuracy of the clock signal.

Thanks,

Miyamoto

[ShunsukeMatsuno]

Have you read Table 59-1 in RM Rev.1?  It clearly specifies SPDIF_SR_CLK can be routed to ENET_REF_CLK pin or GPIO_8 pin.  Regarding the accuracy, it should depend on the SPDIF_IN signal.

1)
Can I understand that “SPDIF Rx Clock” is equal to “SPDIF_SR_CLK”?
If so, customer is able to output “SPDIF Rx Clock” to ENET_REF_CLK pin or GPIO_8 pin.

Answer)
SPDIF Rx Clock should be equal to SPDIF_SR_CLK.

2)
Regarding the accuracy, SPDIF Rx Clock is generated by DPLL in SPDIF Rx block. So I think the accuracy is depend on DPLL. Is my understanding correct?

Answer)
SPDIF Rx Clock is extracted from the SPDIF input bitstream.  That's why I said it depends on the SPDIF_IN signal.

[karina_valencia · Accepted solution]

RaymondChoi Mar 16, 2014 9:00 PM (in response to Shunsuke Matsuno)

Hi,

1) SPDIF Rx Clock should be equal to SPDIF_SR_CLK.

2) SPDIF Rx Clock is extracted from the SPDIF input bitstream.  That's why I said it depends on the SPDIF_IN signal.

Best regards

Raymond

[Aemj]

Hi All,

Sorry for hurrying you up, but the customer needs the answer asap.

BR,

Miyamoto

[Aemj]

Hi,

I am still wait for your reply.

Could you tell me the current progress status?

BR,

Miyamoto