Question, i.MX25 USB

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Aemj
Contributor IV

Hi team,

My customer is working on the circuitry design for their own i.MX25 board.

They have the questions on the connection of USB VBUS.

(1)

In the schematic of i.MX25PDK, it seems that USBPHY1_VBUS pad(K17) of i.MX25 is connected to 5V VBUS.

Is the voltage level of USBPHY1_VBUS 3.3V?

If so, is it alright to connect USBPHY1_VBUS pad to 5V VBUS?

(2)

In the schema of i.MX25PDK, the customer believes that USBH2_PWR is ‘High active’ and USBOTG_PWR is ‘Low active’.

Is it possible to configure the polarity(High active/Low active) of those pins?

Thanks,

Miyamoto

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gusarambula
NXP TechSupport
NXP TechSupport

My apologies for the delay

You are correct; SBH2_PWR is active high output signal. It may be disabled on register HCSPARAMS[PPC] register serves to control this signal You may find more information on this register in section 45.5.2.4.3 of the i.MX25 Reference Manual.

As for the USB_OTG_PWR pin I apologize, you may change its polarity on register USB_CTRL[PP_OTG]. You may find more information on this register’s section of the i.MX25 Reference Manual (47.3.1.1). The PDK does use it as active low.

PS. SBG2_PWR polarity may be changed on register bits USB_CTRL[PP_HST]

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Aemj
Contributor IV

Hi team,

I am still waiting for your comment.

BR,

Miyamoto

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gusarambula
NXP TechSupport
NXP TechSupport

There may be not enough information on the i.MX25 documentation but as reference you can check the i.MX51 Datasheet as the USB PHY works the same.

USBPHY1_VBUS is not a power supply but a comparator so it can support 5V in order to detect the USB 5V supply. When USB OTG operates a HOST this signal is ignored, when it’s working as device mode the status of this signal will be checked. You may go ahead and use a similar con figuration than that of the i.MX25 PDK if it suits your needs.

Unfortunately it is not possible to configure the polarity of the USBH2_PWR and USBOTG_PWR pins. Their behavior is as described on the Reference Manual and while polarity cannot be changed trough registers.

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Aemj
Contributor IV

Hi Gusarambula,


Could you give me your comment please?


BR,

Miyamoto

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gusarambula
NXP TechSupport
NXP TechSupport

My apologies for the delay

You are correct; SBH2_PWR is active high output signal. It may be disabled on register HCSPARAMS[PPC] register serves to control this signal You may find more information on this register in section 45.5.2.4.3 of the i.MX25 Reference Manual.

As for the USB_OTG_PWR pin I apologize, you may change its polarity on register USB_CTRL[PP_OTG]. You may find more information on this register’s section of the i.MX25 Reference Manual (47.3.1.1). The PDK does use it as active low.

PS. SBG2_PWR polarity may be changed on register bits USB_CTRL[PP_HST]

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Aemj
Contributor IV

Hi Gusarambula,


Thanks for your reply.

Let me clarify;

The customer thinks the polarity of USBH2_PWR can be changed by USB_CTRL[PP_HST] register setting.

Correct?


BR,

Miyamoto

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gusarambula
NXP TechSupport
NXP TechSupport

I apologize. You are correct! The USBH2_PWR polarity can be changed using register bits USB_CTRL[PP_HST].

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Aemj
Contributor IV

Hi Gusarambula,

Thanks for your reply.

Sorry, but i cannot find the description about the behavior of USBH2_PWR and USBOTG_PWR.

Could you show me where can i see that?

Is the customer's understanding on the polarity, USBH2_PWR is ‘High active’ and USBOTG_PWR is ‘Low active’, of these pins correct?

Best Regards,

Miyamoto

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Aemj
Contributor IV

Hi Gusarambula,

I am still waiting for your reply.

BR,

Miyamoto

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