Question, i.MX6D PMIC_STBY_REQ

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Question, i.MX6D PMIC_STBY_REQ

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Aemj
Contributor IV

Dear team,

I would like to ask about the behavior of i.MX6D PMIC_STBY_REQ.

My customer is trying to add external WatchDog for the workaround of ERR006282.

They tested whether the watchdog can work fine in the case of boot failure by forced removing input to the WD.

And they saw some i.MX6 chips did output High from PMIC_STBY_REQ when POR = L, and some chips did not.

They expected i.MX6 does not output High from PMIC_STBY_REQ when POR gets asserted.

Is the behavior of PMIC_STBY_REQ reasonable?

Are there any ways to make i.MX6 not output High from PMIC_STBY_REQ at POR=L?

BTW, the customer uses MCIMX6D7CVT08AC.

Thanks,

Miyamoto

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Yuri
NXP Employee
NXP Employee

   Strictly speaking, pin states of i.MX6 during power on sequence and POR
are not defined. In the same time, the PMIC_STBY_REQ of the i.MX6 and
corresponding PMIC MMPF0100 STANDBY signals are fed via coin cell (always  
present) VSNVS supply. So, undefined state of the PMIC_STBY_REQ may
take place only when changing the coin cell. Note, after reset the PMIC_STBY_REQ
is negated (LOW) and the PMIC exits standby mode.

Have a great day,
Yuri

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Aemj
Contributor IV

Hi Yuri,

Thanks for your reply.

What the customer wants to do is to reset i.MX6 without asserting PMIC_STBY_REQ.

Do you have any ideas on that?

BestRegards,

Miyamoto

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Yuri
NXP Employee
NXP Employee

   The erratum workaround provides general idea how to usean external watchdog :
"The user implements an external watchdog [...]. On a successful boot,
the processor toggles the external watchdog through some I/O mechanism
(for example, a GPIO) which prevents the watchdog from firing. If a boot failure
occurs, the external watchdog will expire, thus resetting the processor."
   Unpredictable GPIO pin states should not take place when using MX6 POR signal
for reset under stable power supply voltages (voltage rising has been  finished).

~Yuri.


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Aemj
Contributor IV

Thanks Yuri.

> Using MX6 POR signal for reset under stable power supply voltages(voltage rising has been finished).

As for the above,

Can I understand PMIC_STBY_REQ signal should be disconnected from MMPF0100 in the above situation at least?

BR,

Miyamoto

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