Hello,
> why you say that KPP_ROW6 (V5) pin has no GPIO functionality?
Most of KPP signals can be configured as GPIO via IOMUXC_SW_MUX_CTL_PAD_KPP-...
registers, but the KPP_ROW6 does not have corresponding register.
Only the following ones are available :
IOMUXC_SW_MUX_CTL_PAD_KPP_ROW0
IOMUXC_SW_MUX_CTL_PAD_KPP_ROW1
IOMUXC_SW_MUX_CTL_PAD_KPP_ROW2
IOMUXC_SW_MUX_CTL_PAD_KPP_ROW3
IOMUXC_SW_MUX_CTL_PAD_KPP_COL0
IOMUXC_SW_MUX_CTL_PAD_KPP_COL1
IOMUXC_SW_MUX_CTL_PAD_KPP_COL2
IOMUXC_SW_MUX_CTL_PAD_KPP_COL3
Regards,
Yuri.