Question about CCM_CACRR

[宗標廖]

Hello Community

In page 829 of imx6sdl reference manual(IMX6SDLRM.pdf Rev.2),there is description for arm_podf in CCM_CACRR as bellow.

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NOTE: If arm_freq_shift_divider is set to '1' then any new write to arm_podf will be held until
arm_clk_switch_req signal is asserted.

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I searched arm_freq_shift_divider and arm_clk_switch_req in IMX6SDLRM.pdf, buf cannot find them in anywhere else.

So what does this NOTE mean?

Thank you!

ZongbiaoLiao

[Yuri · Accepted solution]

Hello

  This relates to bit “arm_podf_busy” of CCM Divider Handshake In-Process Register (CCM_CDHIPR) :

Busy indicator for “arm_podf”.

0 - divider is not busy and its value represents the actual division.

1 - divider is busy with handshake process with module. The value read in the divider represents the previous

value of the division factor, and after the handshake the written value of the arm_podf will be applied.

Have a great day,
Yuri

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