QSPI Flash access for MIMXRT1064

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QSPI Flash access for MIMXRT1064

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yamakatb
Contributor III

Hello,

 

I am using the MIMXRT1064 with QSPI flash on IAR with EWARM IDE.

Base project

SDK_2.7.0_EVK-MIMXRT1064\boards\evkmimxrt1064\component_examples\flash_component\flexspi_nor

My QSPI flash manual:

https://www.winbond.com/resource-files/w25q256jv%20spi%20revg%2008032017.pdf

I am using the flexspi_nor project from the EWARM as a base project to test code to program and erase the QSPI flash.

Questions:

1) If chip erase is applied with the sample settings, values other than 0xFF (mostly 0x22) will be written to the first 1Byte of each page.(ADP and ADS bits of QSPI Flash reads "1".)
Also, when the page program was performed and the written address was read again, it was found that the written value was lost by 2 bytes.

Is this a problem with the sequence to register in the LUT?

2) If so, what settings can be changed to read and write correctly?

Any help is appreciated, thanks.

T.Y.

1.After chip erase

pastedImage_1.png

2.Write buffer

pastedImage_3.png

3.Read buffer

pastedImage_2.png

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi ,

Thanks for your reply.
I was wondering if you can share the detailed testing steps and wave signals, it can help me to figure it out.

Have a great day,
TIC

 

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yamakatb
Contributor III

Hi ,jeremyzhou

Thank you for your reply. 

1) Currently testing based on flexspi_nor_polling_transfer.
After sending a command during a test, the phenomenon that SEQIDLE is not cleared often occurs. (Sometimes it is cleared.)
At what timing does this happen?
-->The command setting failed, so I corrected it and succeeded.

With the above, we have confirmed the operation based on flexspi_nor_polling_transfer, so we will proceed with this.

Thank you for supporting me.

Best regards,

T. Y.

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1245366615
Contributor I

The command setting failed, so I corrected it and succeeded

-->hello T.Y. ,I encountered the same problem, could you please show me the detail solution?

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yamakatb
Contributor III

Hi li shaolong,
I reviewed the LUT registration with reference to the QSPI flash data sheet and the attached table.

Wish it helps you!Instruction set (continued).png

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1245366615
Contributor I

Thank you for your reply. I am very helpful.And I have solved the problem.

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yamakatb
Contributor III

jeremyzhou

Hi ,
Thank you for your reply. I am very helpful.
>-After having a brief review of your code, in my opinion, it's a better way to configure the LUT via parsing SFDP table.However, I still suggest you can try to configure the LUT as the flexspi_nor_polling_transfer presents to compare the current method .
--Thank you for your feedback. I will refer to it.

1) Currently testing based on flexspi_nor_polling_transfer.
After sending a command during a test, the phenomenon that SEQIDLE is not cleared often occurs. (Sometimes it is cleared.)
At what timing does this happen?

2)There is still a timing gap at the time of Read / Write.
What exactly does the phenomenon seem to be related to the hardware?

Best regards,

T. Y.

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi ,

Thanks for your reply.
I was wondering if you can share the detailed testing steps and wave signals, it can help me to figure it out.

Have a great day,
TIC

 

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yamakatb
Contributor III

jeremyzhou

Hi ,

Thank you for helping me,

Attached the code.

Is it better to create LUT according to QSPI Flash specification like polling_transfer ...?

Best regards,

T. Y.

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi
Thanks for your reply.
1) Is it better to create LUT according to QSPI Flash specification like polling_transfer?
-- After having a brief review of your code, in my opinion, it's a better way to configure the LUT via parsing SFDP table. However, I still suggest you can try to configure the LUT as the flexspi_nor_polling_transfer presents to compare the current method.
In addition, I suspect the phenomenon may be related to the hardware, you can give a try slow down the flexspiRootClk in flexspi_mem_config_t struct or increase the FlexSPI clock to 130 MHz as the flexspi_nor_polling_transfer does.

Have a great day,
TIC

 

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi ,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
It seems a bit weird, it's hard to say that's a problem with the sequence to register in the LUT.
So whether you can share the actual testing code you run.
Looking forward to your reply.

Have a great day,
TIC

 

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