Problem when Operating IMX6D processor at 996MHz

[rammanohar]

Hello All,

I have question regarding CPU operating at 996MHZ?

My hardware board is having a Imx6 Dual processor & DDR3 supporting 2GB.

The system is stable when I operate the CPU at frequency 900MHZ with GPU, MMU, L1 cache and Branch prediction enabled. But the system aborts when I try to increase my CPU frequency above 900MHz.

To solve this problem I have calibrated the DDR & also ran the DDR stress test overnight and there is no data corruption found and the calibrated values seems to be fine.

But in the processor datasheet it is mentioned that, to operate the cpu at 996MHz it is desired to change the LDO Output set points, Please refer the Datasheet Operating ranges Tabe 6.

I have probed my board to measure both input and the LDO output voltages, and the results are detailed below:

      Inputs:

1. VDD_ARM_IN & VDD_ARM23_IN = 1.425V supplied from PMIC SWA/B
2. VDD_SOC_IN=1.425V supplied from PMIC SWCOutputs:
3. VDD_ARM_CAP & VDD_ARM23_CAP= 1.175Volts
4. VDD_SOC_CAP= 1.170Volts
5. VDD_PU_CAP= 1.170Volts

Please let me do i really need to set the digital LDO outputs to the voltage of 1.250 Volts to operate the CPU frequeny at 996MHz, as they have specified in the datasheet?

Also let me know, what will be  of the default LDO Mode, and if required how to change the mode?

Many Thanks,

Ram

[art]

First, please specify the exact part number of your i.MX6Dual part. The reason is that your part might just not be qualified to operate at 1GHz frequency.

Best Regards,
Artur

[rammanohar]

Hello Artur,

The Chip part number is MCIMX6D6AVT10AD

Thanks,

Ram

[art · Accepted solution]

Yes, the part you specified is qualified to operate at 1GHz core clock frequency. And, yes, you have to set the VDD_ARM linear regulator output (VDD_ARM_CAP rail) to at least 1.225V (better to 1.250V) to make the processor operate at 1GHz core clock frequency. The default power-on output setpoint of the VDD_ARM linear regulator is 1.100V, it further can be changed by appropriately setting the PMU_REG_CORE[REG0_TARG] field. For more information, please refer to the Section 50.7.4 "Digital Regulator Core Register (PMU_REG_CORE)" of the i.MX6Dual/Quad Reference Manual document, available on the processor's Documentation web page:

http://www.nxp.com/products/automotive-products/microcontrollers-and-processors/arm-mcus-and-mpus/i....

Have a great day,
Artur

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[rammanohar]

Thank you Artur.

Cheers,

Ram