Porting DP93869 driver; how to change MDIO address and select DP83869_RGMII_COPPER_ETHERNET?

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Porting DP93869 driver; how to change MDIO address and select DP83869_RGMII_COPPER_ETHERNET?

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Gandalf-kern
Contributor IV

Porting a DP83869 driver to imx8qxp.  My device tree for the phy is given below. It references imx8qxp.dtsi which references imx8-ss-conn.dtsi. 

The eth0 on module phy is has an MDIO address of 5b040000.ethernet.  The eth1 external custom phy using the DP83869 is assumed to have a MDIO address of 5b050000.ethernet inherited from imx8-ss-conn.dtsi.

fec1: ethernet@5b040000 {
reg = <0x5b040000 0x10000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet0_lpcg 4>,
<&enet0_lpcg 2>,
<&enet0_lpcg 3>,
<&enet0_lpcg 0>,
<&enet0_lpcg 1>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
status = "disabled";
};

fec2: ethernet@5b050000 {
reg = <0x5b050000 0x10000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet1_lpcg 4>,
<&enet1_lpcg 2>,
<&enet1_lpcg 3>,
<&enet1_lpcg 0>,
<&enet1_lpcg 1>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
status = "disabled";
};

 

My device tree has the following:

&fec2 {
           //reg = <0x5b000000 0x10000>;
           reg = <0>;
           pinctrl-names = "default";
           pinctrl-0 = <&pinctrl_fec2>;
           compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec";
           fsl,magic-packet;
           fsl,rgmii_rxc_dly;
           fsl,rgmii_txc_dly;
           phy-mode = "rgmii";
           phy-handle = <&ethphy1>;
           enable-active-high;
           regulator-always-on;
           regulator-min-microvolt = <3300000>;
           regulator-max-microvolt = <3300000>;
           phy-reset-gpios = <&gpio_b 9 GPIO_ACTIVE_LOW>;
           phy-reset-duration = <1000>;

           status = "okay";

mdio {
           #address-cells = <1>;
           #size-cells = <0>;
           status = "okay";
           ethphy1: ethernet-phy@1 {

                      interrupt-parent = <&lsio_gpio3>;
                      interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
                      micrel,led-mode = <0>;

                      rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
                      tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
                      ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
                      ti,max-output-impedance = "true";
                      ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
                      rx-internal-delay-ps = <2000>; /* 250 - 4000 in steps of 250 */
                      tx-internal-delay-ps = <2000>;

            }

voltage regulator seems fine, 3.3V on phy enable and 1.8v on MDIO interface. Not seeing the correct MDIO address since device tree defaults to 5 and not address 0.  0 is the default address of the chip for the MDIO address. Also, the DP83869_RGMII_COPPER_ETHERNET op_mode is not being picked up by the driver.

1) How do I change the MDIO address to 0?

2) How do I pass the DP83869_RGMII_COPPER_ETHERNET  property from this device tree to the driver?

I receive the message fec 5b050000.ethernet eth1: Unable to connect to phy.  So, the MDIO address is not zero, it is defaulting to 5 instead? 

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4 Replies

1,409 Views
Gandalf-kern
Contributor IV

Thanks Igor

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1,419 Views
igorpadykov
NXP Employee
NXP Employee

Hi Tracy

 

0x5b040000 is address of ENET module as described in Table 2-5. Connectivity memory map

i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual

 

for mdio reg one can look at documentation and example:

https://source.codeaurora.org/external/imx/linux-imx/tree/Documentation/devicetree/bindings/net/fsl-...

https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8dxl-evk-...

 

Best regards
igor

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1,406 Views
Gandalf-kern
Contributor IV

It appears that the MDIO address is fixed using address 4, which is the on module MDIO address. This is the only address I see traffic. The second phy on the iMX8QXP doesn't pick up the mdio address for the external phy or fec2. 

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1,409 Views
Gandalf-kern
Contributor IV

Not enough information has been provided to help resolve the issue I'm afraid.

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