Peripheral address difference Linux DTS vs NXP UG .. cannot understand it

[dry]

Could some explain this please.. .I'm looking at DTS for my NXP SoC and a COM/board, trying to locate some peripherals and checking addresses.

What I cannot understand is what I see in DTS/Linux addresses vs what they are in SoC User guide, i.e. physical devices per NXP guide. 

So e.g.:

dry_0-1663122559244.png

What I thought / expected to see is something like , for serial 0 as UART1 address i.e :

dry_1-1663122747956.png

As for example in device tree here :

dry_2-1663122804627.png

This is from this link :https://www.emcraft.com/som/imx-8m/using-imx-8m-uart-ports-in-linux

In the above tree I can directly map that UART3 address to the address in the UG, i.e 

dry_3-1663122876357.png

So.. why do I have my serials starting at 0x5a......... ?   

I have similar issue understanding what Linux's shows me for my GPIO ports:

dry_4-1663122968719.png

Again, not addresses per my UG... Where does this come from, how to map to physical addresses to get actual physical peripheral ..?

If this is some standard device tree method to remap these, could you provide a link explaining how this works..?

[dry]

@AldoG 

I'm still lost on it, if you don't mind sending NXP's link to the document / User Guide you referring to? 

The first image is from the actual running system. Yes, it traces as having LPUART.

But the chip you have referred to  i.MX8QM, if I check overview at NXP's site: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-proces...

This has only one 4 core A53 complex, but my booted chip has 6 cores total managed by Linux, so I cannot find one QM variant with 6 cores - presumably A53 + A72 .. ? 

dry_0-1663196083868.png

dry_1-1663196479753.png

Which iMX8 M then has 6 cores ?

[AldoG · Accepted solution]

Hello,

This is actually the problem since you're not using an i.MX8M it is an i.MX8(QM), which is a different processor, sometimes the name causes confusion since it is really similar.

i.MX8(QM) processor webpage
https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-proces...

i.MX8(QM) Reference manual
https://www.nxp.com/webapp/Download?colCode=IMX8QMRM

Best regards,
Aldo.

[dry]

@AldoG Thank you, now its starting to look much better.

dry_0-1663199829618.png

Is there similar one for the GPIO ones ..? I think I'm looking into Low Speed I/O sub-system but I cannot find a similar memory map for that sub-section for my I/O ...

[dry]

.. and answering my own question ...

dry_0-1663200122438.png

Ta daaam

Thank you things starting to look more sensible now!

[AldoG]

Hello,

You have used an incorrect reference both for the reference manual and the example you have found.

From the first image you have shared it is from i.MX8QM and the reference you have used is the i.MX8MQ which is a different processor.

Following the first example, for the i.MX8QM LPUART is part of the DMA subsystem, from the i.MX8QM reference manual chapter 17.8.5.1.1 LPUART memory map:

DMA.lpuart0 base address: 5A06_0000h
DMA.lpuart1 base address: 5A07_0000h

As it is displayed in the device tree.

Best regards,
Aldo.